Reconfigurable Computing and Parallelism for Implementing and Accelerating Evolutionary Algorithms

  • Miguel A. Vega Rodríguez
  • Juan A. Gómez Pulido
  • Juan M. Sánchez Pérez
  • José M. Granado Criado
  • Manuel Rubio del Solar
Part of the Studies in Computational Intelligence book series (SCI, volume 22)


Reconfigurable Computing is a technique for executing algorithms directly on the hardware in order to accelerate and increase their performance. Recon-figurable hardware consists of programmed FPGA chips for working as specific purpose coprocessors. The algorithms to be executed are programmed by means of description hardware languages and implemented in hardware using synthesis tools. Reconfigurable Computing is very useful for processing high computational cost algorithms because the algorithms implemented in a specific hardware get greater performance than if they are processed by a general purpose conventional processor. So Reconfigurable Computing and parallel techniques have been applied on a genetic algorithm for solving the salesman problem and on a parallel evolutionary algorithm for time series predictions. The hardware implementation of these two problems allows a wide set of tools and techniques to be shown. In both cases satisfactory experimental performances have been obtained.


Travel Salesman Problem Travel Salesman Problem Hardware Implementation Recursive Little Square Memory Bank 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer 2006

Authors and Affiliations

  • Miguel A. Vega Rodríguez
    • 1
  • Juan A. Gómez Pulido
    • 1
  • Juan M. Sánchez Pérez
    • 1
  • José M. Granado Criado
    • 1
  • Manuel Rubio del Solar
    • 2
  1. 1.Departamento de Informática, Escuela PolitécnicaUniversidad de Extremadura, Campus Universitario s/nCáceresSpain
  2. 2.Servicio de InformáticaUniversidad de Extremadura, Avda. de Elvas s/nBadajozSpain

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