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A Reconfigurable Parallel Hardware for Genetic Algorithms

  • Nadia Nedjah
  • Luiza de Macedo Mourelle
Part of the Studies in Computational Intelligence book series (SCI, volume 22)

Abstract

In this chapter, we propose a massively parallel architecture of a hardware implementation of genetic algorithms. This design is quite innovative as it provides a viable solution to the fitness computation problem, which depends heavily on the problem-specific knowledge. The proposed architecture is completely independent of such specifics. It implements the fitness computation using a neural network. The hardware implementation of the used neural network is stochastic and thus minimises the required hardware area without much increase in response time. Last but not least, we demonstrate the characteristics of the proposed hardware and compare it to existing ones.

Keywords

Genetic Algorithm Hardware Implementation Genetic Operator Hardware Architecture Systolic Array 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer 2006

Authors and Affiliations

  • Nadia Nedjah
    • 1
  • Luiza de Macedo Mourelle
    • 2
  1. 1.Department of Electronics Engineering and TelecommunicationsFaculty of Engineering, State University of Rio de JaneiroBrazil
  2. 2.Department of Systems Engineering and ComputationFaculty of Engineering, State University of Rio de JaneiroBrazil

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