KeywordsParasitic Capacitance Standard Cell NMOS Transistor Electric Scheme Interconnection Channel
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
Unable to display preview. Download preview PDF.
- E. Charbon, R. Gharpurey, P. Miliozzi, R.G. Meyer, A. Sangiovanni-Vincentelli, SUBSTRATE NOISE — Analysis and Optimization for IC design. Kluwer Academic Publishers, (2001).Google Scholar
- J.M. Cohn, et al., “Analog Device-Level Layout Automation”, Norwell, MA: Kluwer, (1994).Google Scholar
- R.L.M. Dang and N. Shigyo, “Coupling capacitance for two-dimensional wires”, IEEE Electron Deviced Letters, Vol. EDL-2, No. 8, pp. 196–197, (August 1981).Google Scholar
- M. I. Elmasry, “Capacitance calculations in mOSFET VLSI”, IEEE Electron Deviced Letters, Vol. EDL-3, No. 1, pp. 6–7, (January 1982).Google Scholar
- F. Maloberti, “Analog Design for CMOS VLSI System”, Kluwer Academic Publishers, Boston, (2001).Google Scholar
- W. Maly, Atlas of I.C. Technology, The Benjamin Cummings Publishing Company, (1987).Google Scholar
- K. Ming-Dou, W. Chung-Yu, W. Tain-Shun, “Area-Efficient Layout Design for CMOS Output Transistors”, IEEE, Trans. On Electron Devices, vol. 44, no. 4, (April 1997).Google Scholar
- T. Sakurai and K. Tamaru, “Single formulas for two-and three-dimensional capacitances”, IEEE Transactions on Electron Devices, Vol. ED-30, No.2, pp. 183–185, (February 1983).Google Scholar
- N.P. Van Der Meiji, J.T. Fokkema, “VLSI circuit reconstruction from work topology”, North Holland INTEGRATION, the VLSI Journal vol. 2, pp. 85–119, (1984).Google Scholar
© Springer-Verlag Berlin Heidelberg 2005