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The MOSFET Transistor and the Memory Cell

Keywords

Threshold Voltage Gate Voltage Charge Pump NMOS Transistor Gate Current 
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Bibliography

  1. S. Aritome, R. Shirota, G. Hemink, T. Endoh, and F. Masoka, “Reliability issues of Flash memory cells,” Proc. IEEE, vol. 81, no. 5, pp. 776–788, (May 1993).CrossRefGoogle Scholar
  2. R. Bez et al., “Depletion Mechanism of Flash cell induced by parasitic drain stress contidion”, VLSI Technology Symposium, (1994).Google Scholar
  3. J. D. Bude, “Gate current by impact ionization feedback in sub-micron MOSFET technologies”, in 1995 Symposium VLSI Technology Dig. Tech. Pap., pp. 101–102, (June 1995).Google Scholar
  4. J. D. Bude, M.R. Pinto and R. K. Smith, “Monte Carlo Simulation of the CHISEL Flash Memory Cell,” IEEE Tran. Electron Devices, vol. 47, pp. 1873–1881, (Oct. 2000).Google Scholar
  5. E. Burstein, S. Lundqvist, “Tunneling Phenomena in Solida”, Plenum Press, New-York, (1969).Google Scholar
  6. E. Camerlenghi, P. Caprara, and G. Crisenza: “A 18 µm2 cell for megabit CMOS EPROM”, in Proc. 17th European Solid State Device Research Conf., pp. 765–768, (Sept. 1987).Google Scholar
  7. John Y. Chen, CMOS devices and technology for VLSI, Prentice Hall, (1990).Google Scholar
  8. A. Chimenton, P. Pellati, and P. Olivo, “Constant Charge Erasing Scheme for Flash Memories,” IEEE Tran. Electron Devices, vol. 49, pp. 613–618, (Apr. 2002).Google Scholar
  9. A. Chimenton, et al., “Overerase Phenomena: An insight Into Flash Memory reliability”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 617–626, (April 2003).Google Scholar
  10. C. Dunn, C. Kaya, T. Lewis, T. Strauss, J. Schreck, P. Hefley, M. Middendorf, and T. San, “Flash EEPROM disturb mechanisms,” in Proc. Int. Rel. Phys. Symp., pp. 299–308, (April 1994).Google Scholar
  11. B. Eitan and D. Frohman-Bentchkowski, “Hot electron injection into the oxide in n-channel MOS devices”, IEEE Trans. Electron Devices, vol. ED-28, pp. 328–340, (March 1981).Google Scholar
  12. B. Eitan, R. Kazerounian, A. Roy, G. Crisenza, P. Cappelletti, and A. Modelli, “Multilevel Flash cells and their trade-offs”, in 1996 IEDM Tech. Dig., pp. 169–172, (Dec. 1996).Google Scholar
  13. Leo Esaki, “Long Journey into Tunneling”, Proceedings of IEEE, vol 62, No 6, pp 825–835, (June 1974).Google Scholar
  14. D. Frohman-Bentchkowsi, “Memory behavior in a floating gate avalanche-injection MOS (FAMOS) structure”, Appl. Phys. Lett., vol. 18, pp. 332–334, (1971).Google Scholar
  15. D. Frohman-Bentchkowsi, “FAMOS-A new semiconductor charge storage device”, Solid State Electron, vol. 17, pp. 517–520, (1974).Google Scholar
  16. C. Hu, “Lucky-electron model for channel hot-electron emission”, 1979 IEDM Tech. Dig., pp. 22–25, (Dec. 1979).Google Scholar
  17. C. Hu, “Future CMOS scaling and reliability”, Proc. IEEE, vol. 81, pp. 682–689, (May 1993).CrossRefGoogle Scholar
  18. Y. Igura et al., “New Device Degradation Due to "Cold" Carriers Created by Band-to Band Tunneling”, IEEE Electro Device Letters, VOL. 10, NO. 5, MAY (1989).Google Scholar
  19. C. Kittel, Introduction to Solid State Physic, John Wiley & Sons, New York, (1966).Google Scholar
  20. M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2”, J. of Applied Physics, vol. 40, pp. 273–283, (Jan. 1969).Google Scholar
  21. S. Mahapatra, S. Shukuri, and J. Bude, “CHISEL flash EEPROM-Part I: performance and scaling”, IEEE Trans. Electron Devices, vol. ED-49, pp. 1296–1301, (July 2002).Google Scholar
  22. S. Mahapatra, S. Shukuri, and J. Bude, “CHISEL flash EEPROM-Part I: reliability”, IEEE Trans. Electron Devices, vol. ED-49, pp. 1302–1307, (July 2002).Google Scholar
  23. Yohsuka Mochizucki, “Read-disturb Failure in Flash Memory at low field”, Intel reports, Nikkei Electronics Asia, pp. 35–36, (May 1993).Google Scholar
  24. J. Van Houdt, et al., “The HIMOS Flash technology: The alternative solution for low-cost embedded Mmeory”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 627–635, (April 2003).Google Scholar
  25. Samuel Tuan Wang, “On the I-V characteristics of Floating-Gate Mos transistors”, IEEE Transaction on electron devices, Vol ED-26, No 9, September (1979).Google Scholar

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