Minority Carrier Depletion Region Flash Memory Bipolar Transistor Majority Carrier 
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  1. B.T. Ahlport et al., “CMOS?SOS LSI input/output protection networks”, IEEE Transactions on Electron Devices, Vol. ED-25, No. 8, pp. 933–938, (August 1978).Google Scholar
  2. S. H. Cohen, G. Caswell, “An improved input protection circuit for CMOS/SOS ARRAY”, IEEE Transactions on Electron Devices, Vol. ED-25, No. 8, pp. 926–932, (August 1978).Google Scholar
  3. C. Duvvury, et al., “A Synthesis of ESD input protection scheme”, EOS/ESD Symposium Proccedings, pp. 88–98, (1991).Google Scholar
  4. C. Duvvury, et al., “Dymanic gate coupling of NMOS for efficient output ESD protection”, IEEE, IRPS, pp. 141–150, (1992).Google Scholar
  5. W.S. Feng, et al., “MOSFET drain breakdown voltage”, IEEE Electron Device Letters, Vol. EDL-7, No. 7, pp. 449–450, (July 1986).Google Scholar
  6. E. Fujishi, et al., “Optimized ESD protection circuits for high speed CMOS/VLSI”, Custom Integrated Circuits Conference, pp. 569–573, (1984).Google Scholar
  7. F.C. Hsu, R.S. Muller, C. Hu, “A simplified Model of short channel MOSFET characteristics in the breakdown mode”, IEEE Transactions on Electrical Devices, Vol. ED-30, No. 6, pp. 571–576, (June 1983).Google Scholar
  8. G.J. Hu, “A better understanding of CMOS latch-up”, IEEE Transaction on Electron Devices, Vol. ED-31, No. 1, pp. 62–67, (January 1984).Google Scholar
  9. G. Krieger, “Nonuniform ESD current distribution due to improper metal routing”, EOS/ESD Symposium Proccedings, pp. 104–109, (1991).Google Scholar
  10. I.M. Mackintosh, “The electrical characteristichs of silicon P-N-P-N Triodes”, Proceeding of the IRE, pp. 1229–1235, (June 1958).Google Scholar
  11. T.J. Maloney, “Designing MOS inputs and outputs to avoid oxide failure in the charged device model”, EOS/ESD Symposium Proccedings, pp. 220–227, (1988).Google Scholar
  12. P.S. Neelakan Taswany,”MOS scaling effects on ESD-based failure”, IEEE Custom Integrated Circuits Conference, pp. 400–403, (1986).Google Scholar
  13. Troutman, Latch-up in CMOS Technology The problem and Its Cure, Kluwer Academic Publishers, (1986).Google Scholar

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