High-Voltage Management System


Gate Voltage Flash Memory Charge Pump Drain Voltage Program Pulse 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. M. Alam, B. Weir, and P. Silverman, “A future of function or failure?”, IEEE Circuits and Device Magazine, vol. 18, pp. 2–48, (Mar. 2002).Google Scholar
  2. J.C. Chen, T.H. Kuo, L.E. Cleveland, C.K. Chung, N. Leong, Y.K. Kim, T. Akaogi, and Y. Kasa, “A 2.7V only 8Mb×16 NOR Flash memory”, in 1996 Symp. VLSI Circuits Dig. Tech. Pap., pp. 172–173, (Jun. 1996).Google Scholar
  3. M. Dallabora et al., A 20MB/s date rate 2.5V Flash memory with current controlled field erasing for 1M cycle endurance, ISSCC, pp. 396, (1997).Google Scholar
  4. S. Haddad, C. Chang, A. Wang, J. Bustillo, J. Lien, T. Montalvo, and M. Van Buskirk, “An investigation of erase-mode dependent hole trapping in flash EEPROM memory cell”, IEEE Electron Device Letters, vol. EDL-11, pp. 514–516, (Nov. 1990).Google Scholar
  5. L.G. Heller and W.R. Griffin, “Cascode voltage switch logic: a differential CMOS logic family”, in 1984 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., pp. 16–17, (Feb. 1984).Google Scholar
  6. G.J. Hemink, T. Tanaka, T. Endoh, S. Aritome, and R. Shirota, “Fast and accurate programming method for multi-level NAND EEPROMs", in 1995 Symp. VLSI Technology Dig. Tech. Papers., pp. 129–130, (June 1995).Google Scholar
  7. S. Kenney, R. Bez, D. Cantarelli, F. Piccinini, A. Mathewson, and C. Lombardi, “Complete transient simulation of Flash EEPROM devices”, IEEE Trans. Electron Devices, vol. ED-39, pp. 2750–2757, (Dec. 1992).Google Scholar
  8. O. Khouri, I. Motta, R. Micheloni, G. Torelli, “Voltage regulator for low-consumption circuits”, U.S. Patent No. 6,559,627, (May 6, 2003).Google Scholar
  9. V.N. Kynett, M.L. Fandrich, J. Anderson, P. Dix, O. Jungroth, J.A. Kreifels, R.A. Lodenquai, B. Vajdic, S. Wells, M.D. Winston, and L. Yang, “A 90-ns one-million erase/program cycle 1-Mbit Flash memory”, IEEE J. Solid-State Circuits, vol. SC-24, pp. 1259–1264, (Oct. 1989).Google Scholar
  10. I. Motta, et al., “High voltage management in single-supply CHE NOR-TYPE Flash Memories”, IEEE Proceeding of the, Vol. 91, No. 4, pp. 554–568, (Apr. 2003).Google Scholar
  11. R. Micheloni, I. Motta, O. Khouri, and G. Torelli, “Stand-by low-power architecture in a 3-V only 2-bit/cell 64-Mbit Flash memory”, in Proc. 8th IEEE Int. Conf. Electronics, Circuits, and Systems, vol. II, pp. 929–932, (Sept. 2001).Google Scholar
  12. R. Micheloni, M. Zammattio, G. Campardo, “Nonvolatile memory device with hierarchical sector decoding”, US Patent N. 6,456,530, (Sept. 24, 2002).Google Scholar
  13. R. Micheloni, M. Zammattio, G. Campardo, O. Khouri, G. Torelli, “Hierarchical sector biasing organization for Flash memories”, in Records 2000 IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 29–33, (Aug. 2000).Google Scholar
  14. D. Mills, M. Bauer, A. Bashir, R. Fackenthal, K. Frary, T. Gullard, C. Haid, J. Javanifard, P. Kwong, D. Leak, S. Pudar, M. Rashid, R. Rozman, S. Sambandan, S. Sweha, and J. Tsang, “A 3.3V 50MHz synchronous 16Mb flash memory”, in 1995 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., pp. 120–121, (Feb. 1995).Google Scholar
  15. A. Modelli, A. Manstretta, and G. Torelli., “Basic feasibility constraints for multilevel CHE-Programmed Flash memories”, IEEE Trans. Electron Devices, vol. ED-48, pp. 2032–2041, (Sept. 2001).Google Scholar
  16. K. Shimohigashi and K. Seichi, “Low-voltage ULSI design”, IEEE J. Solid-State Circuits, vol. 28, pp. 408–413, (Apr. 1993).CrossRefGoogle Scholar
  17. K. Takeuchi, T. Tanaka, and H. Nakamura, “A double-level-Vth select gate array architecture for multilevel NAND Flash memories”, IEEE J. Solid-State Circuits, vol. SC-31, pp. 602–609, (Apr. 1996).Google Scholar
  18. T. Tanaka, T. Tanzawa, and K. Takekuchi, “A 3.4-Mbyte/sec programming 3-level NAND Flash memory saving 40% die size per bit”, in 1997 Symp. VLSI Circuits Dig. Tech. Papers., pp. 65–66, (Jun. 1997).Google Scholar
  19. G. Torelli and P. Lupi, “An improved method for programming a word-erasable EEPROM”, Alta Frequenza, Vol. LII, pp. 487–494, (Nov./Dec. 1983).Google Scholar
  20. M. Zammattio, I. Motta, R. Micheloni, C. Golla, “Low consumption voltage boost device”, U.S. Patent No. 6.437.636, (Aug. 20, 2002).Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Personalised recommendations