Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Hwang H; Ting W; Kwong D; Lee J (1990) Electrical and reliability characteristics of ultrathin oxynitride gate dielectric prepared by rapid thermal processing in N2O. IEDM Technical Digest, pp. 421–424
Hayashi T; Ohno M; Uchiyama A; Fukuda H; Iwabuchi T; Ohno S (1991) Effectiveness of N2O-nitrided gate oxide for high performance CMOSFETs Electron Devices. IEEE Transactions 38, p. 2711
Tseng HH; Tobin PJ (1993) Thin CVD stacked gate dielectric for ULSI technology. IEDM Technical Digest, pp. 321–324
Okada Y; Tobin PJ; Rushbrook P; DeHart WL (1994) The performance and reliability of 0.4 micron MOSFET's with gate oxynitrides grown by rapid thermal processing using mixtures of N2Oand O2. Electron Devices, Transactions on 41, Issue 2, pp. 191–197
Maiti B; Tobin PJ; Misra V; Hegde R; Reid KG; Gelatos C (1997) High performance 20 Å NO oxynitride for gate dielectric in deep sub-quarter micron CMOS technology. IEDM Technical Digest, pp. 651–654
Liu CT; Lloyd EJ; Ma Y; Du M; Opila RL; Hillenius SJ (1996) High Performance 0.2 um CMOS with 25 Å gate oxide grown on nitrogen implanted Si substrates. IEDM Technical Digest, pp. 499–502
Han LK; Crowder S; Hargrove M; Wu E; Lo SH; Guarin F; Crabb E; Su L (1997) Electrical characteristics and reliability of sub-3 nm gate oxides grown on nitrogen implanted silicon substrates. IEDM Technical Digest, pp. 643–646
Ito T; Nozaki T; Arakawa H; Shinoda M (1979) Thermally grown silicon nitride films for high-performance MNS devices. Appl Phys Lett 32, P. 330
Gross BJ; Krisch KS; Sodini CG (1991) An optimized 850 degrees C low-pressure-furnace reoxidized nitrided oxide (ROXNOX) process Electron Devices, IEEE Transactions 38, pp. 2036–2041
Yang H; Lucovsky G (1999) Integration of ultrathin (1.6 ∼ 2.0 nm) RPECVD oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETs. IEDM Technical Digest, pp. 245–248
Rodder M; Hattangady S; Yu N; Shiau W; Nicollian P; Laaksonen T; Chao C; Mehrotra M; Lee C; Murtaza S; Aur S (1998) A 1.2 V, 0.1 micron gate length CMOS technology: design and process issues. IEDM Technical Digest, pp. 623–626
Nicollian PE; Baldwin GC; Eason KN; Grider DT; Hattangady SV; Hu JC; Hunter WR; Rodder M; Rotondaro ALP. (2000) Extending the reliability scaling limit of SiO2 through plasma nitridation. IEDM Technical Digest, pp. 545–548
Nakajima A; Khosru QDM; Yoshirnoto T; Kidera T; Yokoyama S (2001) Soft breakdown free atomic-layer-deposited silicon-nitride/SiO2 stack gate dielectrics. IEDM Technical Digest, pp. 133–136
Tseng HH; O'Meara D; Tobin PJ; Wang V; Guo X; Hegde R; Yang I; Gilbert P; Cotton R; Hebert L (1998) Reduced gate leakage current and boron penetration of 0.18 µm 1.5V MOSFETs using integrated RTCVD oxynitride gate dielectric. IEDM Technical Digest, pp. 793–796
Wang D; Ma TP; Golz J; Halpern B; Scmitt JJ (1992) High quality MNS capacitors prepared by jet vapor deposition at room temperature. IEEE Electron Device Lett, pp. 482–484
Wang XW; Shi Y; Ma TP; Cui GJ; Tamagawa T; Golz J; Halpern BL; Schmitt JJ (1995) Extending gate dielectric scaling limit by use of nitride or oxynitride. VLSI Technology Digest of Technical Papers, pp. 109–110
Ma TP (1998) Making silicon nitride film a viable gate dielectric Electron Devices, IEEE Transactions on 45, Issue 3, pp. 680–690
Tseng HH; Tsui PGY; Tobin PJ; Mogab J; Khare M; Wang XW; Ma TP; Hegde R; Hobbs C; Veteran J; Hartig M; Kenig G; Wang V; Blumenthal R; Cotton R; Kaushik V; Tamagawa T; Halpern BL; Cui GJ; Schmitt JJ (1997) Application of JVD nitride gate dielectric to a 0.35 micron CMOS process for reduction of gate leakage current and boron penetration. IEDM Technical Digest, pp. 647–650
Song SC; Luan HF; Chen YY; Gardner M; Fulford J; Allen M; Kwong DL (1998) Ultra thin (< 20 Å) CVD Si3N4 gate dielectric for deep-sub-micron CMOS devices. IEDM Technical Digest, pp. 373–376
Yang IY; Gilbert P; Pettinato C; Anderson SGH; Woodruff R; Misra V; Bhat N; Reid K; Lii T; Yuan C; Dyer D; O'Meara D; Collins S; De H; Veeraraghavan S (1998) Optimization of a 0.18 um 1.5 V CMOS technology to achieve 15 ps gate delay. VLSI Technology Digest of Technical Papers, pp. 148–149
Tsui PGY; Tseng HH; Orlowski M; Sun SW; Tobin PJ; Reid K; Taylor WJ (1994) Suppression of MOSFET reverse short channel effect by N2O gate poly reoxidation process. IEDM Technical Digest, pp. 501–504
Perera AH; Smith B; Cave N; Sureddin M; Chheda S; Islam R; Chang J; Song SC; Sultan A; Croen S; Kolagunta V; Shah S; Celik M; Wu D; Yu KC; Fox R; Park S; Simpson C; Eades D; Gonzalea S; Thomas C; Sturtevant J (2000) A versatile 0.13 um CMOS platform technology supporting high performance and low power applications. IEDM Technical Digest, pp. 571–574
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Tseng, HH. (2005). Silicon Oxynitride Gate Dielectric for Reducing Gate Leakage and Boron Penetration Prior to High-k Gate Dielectric Implementation. In: Huff, H., Gilmer, D. (eds) High Dielectric Constant Materials. Springer Series in Advanced Microelectronics, vol 16. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-26462-0_7
Download citation
DOI: https://doi.org/10.1007/3-540-26462-0_7
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-21081-8
Online ISBN: 978-3-540-26462-0
eBook Packages: Chemistry and Materials ScienceChemistry and Material Science (R0)