KPR: A logic programming language-oriented parallel machine
In this paper, we describe the architecture of a multiprocessor system oriented to the logic programming language, called KPR, which can execute a program written in some parallel logic programming languages. The KPR system is controlled on the basis of a new computation model named "Parallel Reduction (PR-) model", which regards execution of a logic program as a combined process of searching assertions and traversing the corresponding AND/OR inference tree. On this PR-model, a logical process is allocated to a node of a process graph that is dynamically produced at execution time. And, the resultant reduction (folding / unfolding) of this AND/OR process graph is executed in parallel. This execution model is implemented by three kinds of processes as follows: (i) ‘Or-process’ for implementing OR-parallelism of a logic program; (ii) ‘Stream-process’ for realizing the AND-parallelism by a stream-pipeline processing method; (iii) ‘Database-process’ for managing an assertion database.
KPR is a heterogeneous-function distributed-processing system, where each process is executed on the specialized processor. The inter-processor network of KPR is realized by a tree-structured topology, each leaf node of which represents a processor element. The processor element is a tightly-coupled processor pair, called ORP (Or Reduction Processor) and ARP (And Reduction Processor). An intermediate network node is called NNU (Network Node Unit) and is provided with a bus-switching mechanism, status flag registers and a shared memory for storing global environment data. Some DBP's (DataBase Processors) will be attached to some of NNU's and the SVP (Super Visory Processor) will be attached to the root NNU.
An ARP is composed of a PCU-A (Process Control Unit for ARP) which controls process executions and inter-process (processor) communications, and an ARU (And Reduction Unit) which implements a Stream-parallel processing strategy. An ORP is composed of a PCU-O (PCU for ORP) and ORU (Or Reduction Unit) where four sets of unification operations can be executed in parallel by means of four UU's (Unification Units).
KeywordsParallel Inference Machine High-Level Language Machine Logic Programming Language Parallel Processing
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- [Shi86]Shibayama, K. et al.: The Architecture of a Logic Programming-Oriented Parallel Reduction Machine KPR, IEICE Technical Report, EC85–70, pp.43–54 (Mar. 1986). (in Japanese)Google Scholar
- [Shi87]Shibayama, K.: Symbolic Manipulation Machine, Journal of IPS Japan, 28, 1, pp.27–46 (Jan. 1987). (in Japanese)Google Scholar
- [War83]Warren, D.H.D.: An Abstract Prolog Instruction Set, Report of Stanford University Computer Science Department, SRI-309, pp.1–30 (Oct. 1983).Google Scholar