Multipath hierarchies in interconnection networks
In this paper we presented a new approach to interconnection networks for high-performance multiprocessor systems. First, we examined the functions performed by interconnection networks, in general, and identified the delays that are limiting factors to the performance of conventional multistage networks. Then we proposed a network structure which optimizes the delays of each network function, by separating the control flow from the data flow and transmitting the control information through a hierarchy of physical paths with varying transfer speeds. We showed that the control hierarchy could be implemented by using fast networks provided by crossbars and slower networks provided by Δ-nets. Finally, we presented the results of a feasibility study, which showed that the hierarchical control networks are realizable with current VLSI technology.
KeywordsInterconnection Network Collision Detection Memory Module Hierarchical Network Contention Resolution
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