High speed interconnection using the clos network

  • William A. PayneIII
  • Fillia Makedon
  • W. Robert Daasch
Session 2: Parallel Architectures
Part of the Lecture Notes in Computer Science book series (LNCS, volume 297)


This paper discussed two aspects of the use of the Clos networks for high capacity statistical switching. A self routing algorithm was described for the general s staged Clos network, as well as for a special case of the Clos network for which the routing is simpler. The topological VLSI area complexity of the Clos network was also studied and was found to be comparable in many instances to that of the crossbar network. This is true even though the number of crosspoints in the Clos network is usually less than that of the crossbar.


Middle Stage Area Complexity Switch Node Bell System Technical Journal Clos Network 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    C. Clos, "A Study of Non-Blocking Switching Networks," Bell System Technical Journal No. 32, pp. 406–424, 1953.Google Scholar
  2. [2]
    D. Nassimi and S. Sahni, "A Self-Routing Benes Network and Parallel Permutation Algorithms," IEEE Trans. on Comp., Vol. C-30, No. 5, May 1981, pp. 332–340.Google Scholar
  3. [3]
    K. E. Batcher, "Sorting Networks and Their Applications," Proc. AFIPS 1968 SJCC, Vol. 32, AFIPS Press, pp. 307–314.Google Scholar
  4. [4]
    W. A. Payne, Complexity and Performance of Statistically Switched Interconnection Networks, PhD Dissertation, Dept. of Elec. Eng., Illinois Inst. of Tech., 1986.Google Scholar
  5. [5]
    V. E. Benes, "Algebraic and Topological Properties of Connecting Networks," Bell System Technical Journal No. 41, 1962.Google Scholar
  6. [6]
    V. E. Benes, Mathematical Theory of Connecting Networks and Telephone Traffic, Academic Press, 1965.Google Scholar
  7. [7]
    C. D. Thompson, A Complexity Theory for VLSI, Phd Dissertation, Dept. of Comp. Sci., Carnegie-Mellon Univ., 1980.Google Scholar
  8. [8]
    D. Hoey and C. E. Leiserson, "A Layout for the Shuffle-Exchange Network," Proc. of the 1980 IEEE Int. Conf. on Parallel Processing, August 1980.Google Scholar
  9. [9]
    D. Kleitman, F. T. Leighton, M. Lepley, and G. L. Miller, "New Layouts for the Shuffle-Exchange Graph," Proc. 13th ACM Symp. on the Theory of Computing, May 1981.Google Scholar
  10. [10]
    F. T. Leighton, "Optimal Layouts for Small Shuffle-Exchange Graphs," VLSI 81, edited by John P. Gray, Academic Press, London, August 1981.Google Scholar
  11. [11]
    F. T. Leighton, Layouts for the Shuffle-Exchange Graph and Lower Bound Techniques for VLSI, PhD Dissertation, MIT, June 1982.Google Scholar
  12. [12]
    L. R. Goke and G. J. Lipovski, "Banyan Networks for Partitioning Multiprocessor Systems," Proc. 1st Annual Computer Architecture Conference, Dec. 1973.Google Scholar
  13. [13]
    M. Franklin, "VLSI Performance Comparison of Banyan and Crossbar Communications Networks," IEEE Trans. on Computers, April 1981.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1988

Authors and Affiliations

  • William A. PayneIII
    • 1
  • Fillia Makedon
    • 2
  • W. Robert Daasch
    • 3
  1. 1.AT&T Bell LaboratoriesNaperville
  2. 2.Illinois Institute of TechnologyChicago
  3. 3.Illinois Institute of TechnologyChicago

Personalised recommendations