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Performance analysis for a join processor

  • Guang-sheen Liu
  • Huei-huang Chen
Session 10: Algorithms, Architectures And Performance III
Part of the Lecture Notes in Computer Science book series (LNCS, volume 297)

Abstract

An architecture which not only elliminates cross referencing but also maintains ordering reservation (suitable for non-equijoin operation) is proposed. The techniques such as parallel processing and pipelining are applied to greatly enhance the system performance. Response time is derived, by comparing the speed of hardware modules, and analyzed for the efficient evaluation of the join operation on the system architecture.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1988

Authors and Affiliations

  • Guang-sheen Liu
    • 1
  • Huei-huang Chen
    • 2
  1. 1.Department of Electrical EngineeringTatung Institute of TechnologyTaipeiTaiwan, Republic of China
  2. 2.Department of Information EngineeringTatung Institute of TechnologyTaipeiTaiwan, Republic of China

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