A Wavefront Array Processor using dataflow processing elements

  • John A. Vlontzos
  • S. Y. Kung
Session 8: Vlsi, Dataflow And Array Processors
Part of the Lecture Notes in Computer Science book series (LNCS, volume 297)


In this paper, a prototype Wavefront Array Processor based on the NEC μPD7281 dataflow chip is presented. The interconnections of this array are reconfigurable and its processor addressing scheme permits construction of very large arrays. The programming methodology and high level language are presented. These, facilitate the expression and mapping of linear algebra and signal/image processing algorithms on this array. To illustrate the performance and programming of this machine some indicative applications are discussed.


Module Number Dependency Graph High Level Language Interface Chip Output Queue 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    S.Y. Kung, "VLSI Array Processors", Prentice Hall 1987.Google Scholar
  2. 2.
    "μPD7281 User's Guide", NEC Electronics 1985.Google Scholar
  3. 3.
    "μPD9305 (Magic) User's Guide", NEC Electronics 1985.Google Scholar
  4. 4.
    Karp, R.M., Miller, R.E., Winograd, S. "The Organization of Computations for Uniform Recurrence Equations", Journal of ACM, vol. 14, no. 3, 1967, pp 563–590.Google Scholar
  5. 5.
    Rao, S.K., "Regular Iterative Algorithms and their Implementation on Processor Arrays", Ph.D. Thesis, Stanford University 1985.Google Scholar
  6. 6.
    Backus, J., "Can Programming be Liberated from the Von Neumann Style" Communications ACM, vol. 21, No. 8, Aug. 1978.Google Scholar
  7. 7.
    McGraw, J., Skedzielewski, S., et al., "Sisal Reference Manual" Lawrence Livermore Laboratory 1985.Google Scholar
  8. 8.
    Gurd, J., Watson, I., "Preliminary Evaluation of a Prototype Dataflow Computer", Proc. IFIP, 1983.Google Scholar
  9. 9.
    Gaudiot, J.L., Dubois, M., Lee, L.T., Tohme, N., "The TX16: A Highly Programmable Multimicroprocessor Architecture", IEEE Micro, Oct. 1986.Google Scholar
  10. 10.
    Skedzielewski, et. al. "IF1 Reference Manual", Lawrence Livermore Laboratory 1985.Google Scholar
  11. 10.
    Hudak, P., Smith, L., "Para-Functional Programming: A Paradigm for Programming Multiprocessor Systems", 12th ACM Symp. on Principles of Programming Languages, Jan. 1986, pp 243–254.Google Scholar
  12. 12.
    Ackerman, W.B., Dennis, J.B., "VAL — A value oriented algorithmic language", Tech. Rep. TR-218, Lab. for Computer Science,MIT, June 1979.Google Scholar
  13. 13.
    Arvind, Gostelow, K.P., Plouffe, W., "An Asynchronous Programming Language and Computing Machine" TR 114a, Dept. of Info. and Comp. Sci., Univ. of California, Irvine, Dec. 1978.Google Scholar
  14. 14.
    Dewilde, P., Annevelink, J., "Hierarchical Design of Processor Arrays, Applied to a New Pipelined Matrix Solver", VLSI Signal Processing II, IEEE Press, Nov. 1986.Google Scholar
  15. 15.
    Shapiro, E., "Concurrent Prolog: A Progress Report", IEEE Computer, Vol. 19, No. 8, Aug. 1986.Google Scholar
  16. 16.
    Newman, W.M., Sproull, R.F., "Principles of Interactive Computer Graphics", McGraw Hill 1973.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1988

Authors and Affiliations

  • John A. Vlontzos
    • 1
  • S. Y. Kung
    • 1
  1. 1.Department of Electrical EngineeringUniversity of Southern CaliforniaUSA

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