VLSI arrays with reconfigurable buses

  • Dionisios Reisis
  • V. K. Prasanna Kumar
Session 8: Vlsi, Dataflow And Array Processors
Part of the Lecture Notes in Computer Science book series (LNCS, volume 297)


In this paper we consider mesh connected computers with reconfigurable buses. The architecture consists of N1/2 × N1/2 PEs, with PEs in each row and column connected to a shared bus. The buses are partitionable using N1/2-1 switches embedded on each bus. This provides efficient global communication patterns for a variety of partitions of the mesh connected computer. We illustrate the suitability of the architecture by demonstrating efficient parallel solution to several graph problems and low level vision problems which have low interprocessor communication requirements. Compared to known reconfigurable architectures and other parallel architectures such as mesh of trees and pyramids, the proposed organization has low area requirement and simple switch control while providing fast parallel solutions to several problems.


Data Movement Reconfigurable Architecture Parallel Random Access Machine VLSI Array Reconfigurable Array 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1988

Authors and Affiliations

  • Dionisios Reisis
    • 1
  • V. K. Prasanna Kumar
    • 1
  1. 1.Department of Electrical Engineering-SystemsUniversity of Southern CaliforniaLos AngelesU.S.A.

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