Supercomputing pp 732-743 | Cite as

VLSI arrays with reconfigurable buses

  • Dionisios Reisis
  • V. K. Prasanna Kumar
Session 8: Vlsi, Dataflow And Array Processors
Part of the Lecture Notes in Computer Science book series (LNCS, volume 297)


In this paper we consider mesh connected computers with reconfigurable buses. The architecture consists of N1/2 × N1/2 PEs, with PEs in each row and column connected to a shared bus. The buses are partitionable using N1/2-1 switches embedded on each bus. This provides efficient global communication patterns for a variety of partitions of the mesh connected computer. We illustrate the suitability of the architecture by demonstrating efficient parallel solution to several graph problems and low level vision problems which have low interprocessor communication requirements. Compared to known reconfigurable architectures and other parallel architectures such as mesh of trees and pyramids, the proposed organization has low area requirement and simple switch control while providing fast parallel solutions to several problems.


Data Movement Reconfigurable Architecture Parallel Random Access Machine VLSI Array Reconfigurable Array 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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6. References

  1. [BATC 68]
    K. Batcher, ”Sorting Networks and their Applications”, Spring Joint Computer Conference 32, pp 307–314, AFIPS PRESS, Montwole NJ, 1968.Google Scholar
  2. [BERM 83]
    F. Berman, ”Parallel Computations with Limited Resources”, In Proceedings of the Conf. on Information Sciences and Systems, John Hopkins University, 1983.Google Scholar
  3. [BERM 84]
    F. Berman and L. Snyder, ”Parallel Programming and the Pocket Programming Environment”, Computer 17(7):27–36, July 1984.Google Scholar
  4. [BOKH 84]
    S. H. Bokhari, ”Finding Maximum on an Array Processor with a Global Bus”, IEEE Transactions on Computers, Vol. C-33, No. 2, February 1984, pp 133–139.Google Scholar
  5. [CARL 85]
    D. Carlson, ”The mesh with a Global mesh: A flexible high speed organization for parallel computation”, Tech. Report, Electrical & Computer Engineering dpt., University of Massachusetts, 1985.Google Scholar
  6. [CUNY 84]
    J.E. Cuny and L. Snyder, ”Testing the Coordination Predicate”, Trans. on Computers, C-33(3):201–208, IEEE, March, 1984.Google Scholar
  7. [DAVI 84]
    R. Davis and D. Thomas, ”Systolic Array chip matches the pace of high speed processing”, Electronic design, October 1984.Google Scholar
  8. [DUFF 76]
    M. J. Duff, ”A large scale integrated circuit image processor”, Proc. IJCPR, 1976.Google Scholar
  9. [DYER 81]
    C. R. Dyer, ”A VLSI pyramid machine for hierarchical parallel image processing”, Proc. IEEE conference on Pattern Recognition and Image Processing, 1981.Google Scholar
  10. [GANN 81]
    D. Gannon and L. Snyder, ”Linear Recurrence Systems for VLSI: The Configurable, Highly Parallel Approach”, In Proceedings of ICPP, pp. 259–260, IEEE, 1981.Google Scholar
  11. [GOPA 85]
    P. S. Gopalakrishnan, I. V. Ramakrishnan, L. N. Kanal, ”An Efficient Connected Components Algorithm on a Mesh-Connected Computer”, Tech. Report, Dept of Computer Science, 1985, University of Maryland.Google Scholar
  12. [HEDL 82]
    Kye S. Hedlund and L. Snyder, ”Wafer Scale Integration of Configurable, Highly Parallel Processors”, In Proceedings of ICPP, pp. 262–264, IEEE, 1982.Google Scholar
  13. [HIRS 79]
    D. S. Hirschberg, A. K. Chandra and D. V. Sarwate, ”Computing connected components on parallel computers”, Communications of ACM, 1979.Google Scholar
  14. [JAJA 84a]
    J. Ja'Ja' and V. K. Prasanna Kumar, ”Information Transfer in Distributed Computing with Applications to VLSI”, Journal of ACM, Jan. 1984.Google Scholar
  15. [JAJA 84b]
    J. Ja'Ja', V. K. Prasanna Kumar and J. Simon, ”Information transfer under different sets of protocols”, SIAM Journal on Computing, 1984.Google Scholar
  16. [KUNG 77]
    H. T. Kung and C. D. Thompson, “Sorting on a Mesh Connected Computer”, Comm ACM, 1977.Google Scholar
  17. [LGHT 82]
    F. T. Leighton, “Parallel computations using Mesh of Trees”, Technical Report MIT, 1982.Google Scholar
  18. [MILL 84a]
    R. Miller and Q. F. Stout, “Convexity algorithms for pyramid computers”, Proc. 1984 International Parallel Processing Conference.Google Scholar
  19. [MILL 84b]
    R. Miller and Q. F. Stout, “Computational Geometry on a Mesh-Connected Computer”, Proc. 1984 International Conference on Parallel Processing, pp. 66–74.Google Scholar
  20. [MILL 87]
    R. Miller and Q. Stout, “Data Movement techniques for the Pyramid Computer”, SIAM journal on computing, Vol. 16, No. 1, February 1987.Google Scholar
  21. [NASS 81]
    D. Nassimi and S. Sahni, “Data Broadcasting in SIMD Computers”, IEEE Transactions on Computers 1981.Google Scholar
  22. [NATH 83]
    D. Nath, S. N. Maheshwari, P. C. Bhat, “Efficient VLSI networks for parallel processing based on orthogonal trees”, IEEE, Transactions on Computers, 1983.Google Scholar
  23. [OVER 80]
    M. H. Overmars and J. Van Leeuwen, “Dynamically maintaining configurations in the plane”, Proceedings of the 12th Symposium on Theory of Computing, 1980.Google Scholar
  24. [PRAS 83]
    V. K. Prasanna Kumar, “Communication Complexity of various VLSI Models”, Ph. D. thesis, Dept. of Computer Science, Pennsylvania State Univ., 1983.Google Scholar
  25. [PRAS 85]
    V. K. Prasanna Kumar and C. S. Raghavendra, “Array Processor with Multiple Broadcasting”, Proceedings of the 1985 Annual Symposium on Computer Architecture, June 1985.Google Scholar
  26. [PRAS 86]
    V. K. Prasanna Kumar and Mehrnoosh Eshaghian, “Parallel Geometric algorithms for Digitized pictures on the Mesh of Trees organization”, International Conference on Parallel Processing, 1986.Google Scholar
  27. [PRAS 87]
    D. Reisis and V. K. Prasanna Kumar, “VLSI Arrays with Reconfigurable Buses”, Technical Report, Computer Research Institute University of Southern California, May 1987.Google Scholar
  28. [PRAS 87b]
    V. K. Prasanna Kumar and D. Reisis, “Parallel Image Processing on Enhanced Arrays”, Proceedings of the International Conference on Parallel Processing, 1987.Google Scholar
  29. [ROSE 83]
    A. Rosenfeld, “Parallel Processors for Image Processing: 2-D arrays and extensions”, IEEE Computer, Jan. 1983.Google Scholar
  30. [SHIL 82]
    Y. Shiloach and U. Vishkin, “A O (logN) Parallel Connectivity Algorithm”, Journal of Algorithms 3, 1982.Google Scholar
  31. [SNYD 82]
    L. Snyder, “Introduction to the Configurable, Highly Parallel Computer”, Computer 1S(1):47–56, January, 1982.Google Scholar
  32. [STOU 83]
    Q. F. Stout, “Mesh Connected Computers with Broadcasting”, IEEE Trans. on Computers, pp. 826–830, 1983.Google Scholar
  33. [TANI 83]
    S. L. Tanimoto, “A Pyramidal approach to Parallel Processing”, Proc. 1983 International Symposium on Computer Architecture.Google Scholar
  34. [UHR 84]
    L. Uhr, “Algorithm-Structured Computer Arrays and Networks”, Academic Press, 1984.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1988

Authors and Affiliations

  • Dionisios Reisis
    • 1
  • V. K. Prasanna Kumar
    • 1
  1. 1.Department of Electrical Engineering-SystemsUniversity of Southern CaliforniaLos AngelesU.S.A.

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