Supercomputing pp 716-731 | Cite as

A systolic array structure for matrix multiplication in the residue number system

  • Christos A. Papachristou
  • Suntae Hwang
Session 8: Vlsi, Dataflow And Array Processors
Part of the Lecture Notes in Computer Science book series (LNCS, volume 297)


This paper describes a new scheme for matrix multiplication in the residue number system (RNS) by a VLSI systolic structure. The basic goal is to accelerate matrix multiplication by exploiting the "double parallelism" involved in the systolic structure and in the RNS. The scheme consists of a N × N rhombus-like array of residue-based processors for RNS N × N matrix multiplication. Each processor operates in parallel, pipeline or hybrid modes using an arrangement of q moduli adders and multipliers, q>1. The operations of residue addition and multiplication are performed by associative table lookup processing, which has been shown to be particularly efficient for fast residue arithmetic implementations in VLSI technology.

The time performance of this method was shown experimentally to be very good for large matrix multiplications. Thus, the proposed scheme could be very attractive in special purpose signal processing computers that require a lot of fast linear operations.


Matrix Multiplication Table Lookup Systolic Array Residue Number System VLSI Technology 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1988

Authors and Affiliations

  • Christos A. Papachristou
    • 1
  • Suntae Hwang
    • 1
  1. 1.Computer Engineering and Science Department Center for Automation and Intelligent SystemsCase Western Reserve UniversityClevelandU.S.A.

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