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Design and scheduling of mesh array of hardware unifiers for large-scale unification

  • Yifong Shih
  • Keki B. Irani
Session 8: Vlsi, Dataflow And Array Processors
Part of the Lecture Notes in Computer Science book series (LNCS, volume 297)

Abstract

We propose a hardware unification array consisting of k × n fourconnected unification units to be used to speed up the process of finding suitable bindings for common variables among the predicates in a logic program. Four different algorithms (SIMPLEX, PCC, PwFLP and CP) to perform unification in the array are presented and their performances compared. The final level of unification in scheduling multiple arrays is found to be the most expensive, deserving the highest degree of hardware support.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1988

Authors and Affiliations

  • Yifong Shih
    • 1
  • Keki B. Irani
    • 1
  1. 1.Computing Research Laboratory Department of Electrical Engineering and Computer ScienceThe University of MichiganAnn Arbor

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