Built-in self-testing of logic circuits using imperfect duplication

  • R. Kh. Latypov
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 278)


The method of built-in self-testing is proposed using imperfect duplication. As an example reducing the value of the average probability of missing a fault in the case of BIST of single-output combinational circuit has been shown.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Горяшко А.П., Литвиненко Н.Н., Поспелов Л.В., Пожаров И.И. Системы тестового контроля современных ЗВМ. Обзор основных направлений, Изд. АН СССР, Техн. кибернетика, No. I (1985), 37–56.Google Scholar
  2. 2.
    McClaskey E.J. Built-in self-test techniques, IEEE Des. and Test Comput., vol.2, N 2 (1985), 21–28.Google Scholar
  3. 3.
    McClaskey E.J. Verification testing — a pseudoexhaustive test technique, IEEE Trans. Comput., vol. C-33, N 6 (1984), 541–545.Google Scholar
  4. 4.
    Agarwal V.K. Increasing effectiveness of built-in testing by out-put data modification, 13th Annu.Int.Simp. on FTCS (1983), 227–234.Google Scholar
  5. 5.
    Латыпов Р.Х. Применение кодов Рида-Маллера при самотецтировании схем, Автоматика и телемеханика, No. 9 (1986), 145–151.Google Scholar
  6. 6.
    Golomb S. Shift register sequences, Holden-Day Inc., (1967).Google Scholar
  7. 7.
    Berlecamp E.R., Welch L.R. Weight distribution of the cosets of the (32,6) Reed-Muller code, IEEE Trans. Inform. Theory, vol. IT-18, N 1 (1972), 203–207.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1987

Authors and Affiliations

  • R. Kh. Latypov
    • 1
  1. 1.Kazan state universityUSSR

Personalised recommendations