Implementing logical variables on a graph reduction architecture

Abstract

Logical variables offer a semantic meeting ground between functional and logic programming languages. That is, if functional languages are extended to do parameter passage by unification, much of the power of AND-parallel logic programming is obtained. However, multi-path search, by OR-parallelism or backtracking, remains the province of logic programming.

We outline an implementation strategy for FGL+LV, a functional language with logical variables, on the Rediflow multiprocessing graph reduction architecture. The aspects of logical variables receiving special consideration include:

• a. parallel unification, especially proper treatment of indeterminate behavior, e.g. mutual exclusion on variable binding;

• b. variable binding through emulated graph node merging;

• c. exploitation of two levels of demand: assertive (during unification), and non-assertive (ordinary “read-only” usage), and

• d. avoidance of meaningless cyclic variable bindings.

The existing base language implementation can be smoothly extended, with a word size increase of only one bit (needed to implement two levels of demand). Lazy evaluation in the base language is retained, except that actual parameters are now made strict to one level of evaluation. This requirement, overlooked in a previous paper on this subject, is argued to be semantically and operationally inescapable in a functional language with logical variables. It also provides insight into the vexing problem of how to apply the occur check in a language with infinite data objects. A novel technique for merging cyclic lists is used to implement logical variable binding in a distributed manner without locking or busy waiting.

This material is based upon work supported by NSF Grant DCR-8506000, and a Shared University Research Grant from the IBM Corporation.