Graph reduction in a parallel virtual memory environment
This paper discusses the problems of implementing a parallel machine architecture to support graph reduction. In particular it examines the area of memory organization and the mechanisms which are required to ensure that the full benefits of this implementation strategy are maintained whilst achieving an efficient physical structure. The major areas of interest are the maintenance of locality and the use of storage management techniques which minimize communication.
KeywordsParallel Machine Computational Graph Virtual Memory Graph Reduction Machine Structure
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