Overview of Rediflow II development

  • Robert M. Keller
  • Jon W. Slater
  • Kevin T. Likes
Graph Reduction Architectures
Part of the Lecture Notes in Computer Science book series (LNCS, volume 279)


A status report is provided on the design of Rediflow II, a proposed multiprocessor architecture based on graph reduction. We emphasize recent work on hardware design to support graph reduction, communication, and load balancing, as well as indicating an evaluation model oriented toward larger grain computation than in our previously-reported work.


Load Balance Forward Packet Register File Parallel Evaluation Graph Reduction 
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Copyright information

© Springer-Verlag Berlin Heidelberg 1987

Authors and Affiliations

  • Robert M. Keller
    • 1
  • Jon W. Slater
    • 2
  • Kevin T. Likes
    • 3
  1. 1.Quintus Computer Systems, Inc.Mountain View
  2. 2.ESL, Inc.Sunnyvale
  3. 3.University of UtahSalt Lake City

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