Toward the design of a parallel graph reduction machine the MaRS project

  • Michel Castan
  • Guy Durrieu
  • Bernard Lecussan
  • Michel Lemaître
  • Alessandro Contessa
  • Eric Cousin
  • Paulino Ng
Graph Reduction Architectures
Part of the Lecture Notes in Computer Science book series (LNCS, volume 279)


We have presented our stepwise approach to the design of an architecture for a multiprocessor reduction machine, starting from requirements induced by the language and by architectural considerations.

Perhaps the most important feature of the machine is the load balancing mechanism, that includes the decentralized computation and distribution of an instantaneous load information, allowing tasks to be equally distributed among processors. Furthermore, this load information allows each reduction processor to dynamically change its execution model, thus contributing to the regulation of the instantaneous parallelism in the machine. We also saw how information concerning management of potential parallelism can be conveyed by combinators themselves.

More details of this architecture, such as the network organization, garbage collector, etc., and details concerning compilation, can be found in [Castan85, Castan86a, Castan86b, Lemaître86].


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Copyright information

© Springer-Verlag Berlin Heidelberg 1987

Authors and Affiliations

  • Michel Castan
    • 1
  • Guy Durrieu
    • 1
  • Bernard Lecussan
    • 1
  • Michel Lemaître
    • 1
  • Alessandro Contessa
    • 1
  • Eric Cousin
    • 1
  • Paulino Ng
    • 1
  1. 1.ONERA-CERT — Department of Computer ScienceToulouse CEDEXFRANCE

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