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The D-RISC—An architecture for use in multiprocessors

  • T. J. W. Clarke
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 274)

Abstract

This paper explores the relationship between latency, bandwidth, concurrency and CPU performance using both theory and concrete design analysis. The results are applied to uniprocessors, where they suggest a new CPU architecture, and multiprocessor systems, where this architecture is shown to be particularly effective.

A model of asynchronous concurrency using threads which may be created, referenced and read is used to analyse and contrast dataflow and von Neumann CPU design. Dataflow CPUs are constrained by fetch bandwidth, von Neumann CPUs by fetch latency. A simple quantitative theory of VLSI CPU implementation shows that latency and bandwidth constraints may be balanced, increasing performance, by choosing the right concurrency. This motivates the D-RISC architecture, a hybrid of RISC and dataflow machines using dataflow-like thread-switching to hide cache miss latency.

Keywords

Multiprocessor System Concurrent Execution Bandwidth Constraint Dataflow Graph Concurrent Thread 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1987

Authors and Affiliations

  • T. J. W. Clarke
    • 1
  1. 1.Computer LaboratoryCambridge UniversityUK

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