Abstract
The parallel inference machine (PIM) is the most important hardware research target of the FGCS project. The initial stage mainly aimed to conduct R&D of individual component technologies by studying parallel inference mechanisms from various standpoints. Three basic mechanisms for PIM were studied by software simulators and by developing experimental machines with about 16 modules: the reduction mechanism, the data flow mechanism and the kabu-wake method. PIM R&D in the initial stage revealed the structures and characteristics important to an effective PIM. It also clarified many of the problems associated with the development of more practical experimental systems. In the intermediate stage, both parallel hardware mechanisms and parallel software systems will be studied based on a philosophy that integrates both the hardware and software aspects of the research. Component hardware modules will be developed with the accumulation of implementation techniques such as appropriate hardware building blocks and common software tools. Realistic software research environments will be provided by connecting PSIs to encourage kernel language implementation and parallel operating system development. Efforts to integrate them into a total PIM system will start around the middle of the intermediate stage.
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Goto, A., Uchida, Si. (1987). Toward a high performance parallel inference machine — The intermediate stage plan of PIM —. In: Treleaven, P., Vanneschi, M. (eds) Future Parallel Computers. Lecture Notes in Computer Science, vol 272. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-18203-9_9
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DOI: https://doi.org/10.1007/3-540-18203-9_9
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