Fault-tolerance in parallel architectures

  • M. G. Sami
  • N. Scarabottolo
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 272)


Interconnection Network Systolic Array Switching Element Array Architecture Multistage Interconnection Network 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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6. References

  1. [1]
    K.E. Batcher, "Architecture of a Massively Parallel Processor", Proc. 7th Symp. on Computer Architecture, pp. 168–173, IEEE (May 1980)Google Scholar
  2. [2]
    Special issue, "Interconnection networks", IEEE Computer Magazine, vol. 14, n. 12 (Dec. 1981)Google Scholar
  3. [3]
    T.Y. Feng, "A survey of interconnection networks", IEEE Computer, vol. 14, n. 12, pp. 12–27 (Dec.1981)Google Scholar
  4. [4]
    V. Cherkassky, E. Opper, M. Malek, "Reliabilty and fault diagnosis analysis of fault-tolerant multistage inteconnection networks", Proc. FTCS 14, pp. 246–251, IEEE (June 1984)Google Scholar
  5. [5]
    D.P. Agrawal, "Testing and Fault Tolerance of Multistage Interconnection Networks", IEEE Computer Magazine, vol. 15, n. 4, pp. 41–53 (Apr. 1982)Google Scholar
  6. [6]
    J.P. Shen, J.P. Hayes, "Fault tolerance of dynamic-full-access interconnection networks", IEEE Trans. on Comp., vol. C-33, n. 3, pp. 241–248, IEEE (March 1984)Google Scholar
  7. [7]
    G.B. Adams, H.J. Siegel, "The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems", IEEE Trans. on Computers, vol. C-31, n. 5, pp. 443–454 (May 1982)Google Scholar
  8. [8]
    N.F.Tzeng, P.C.Yew, C.Q.Zhu, "A Fault-Tolerant Scheme for Multistage Interconnection Networks", Proc. 12th Annual International Symposium on COMPUTER ARCHITECTURE, pp. 368–375, IEEE, Boston, MAS (Jun. 1985)Google Scholar
  9. [9]
    J.A.B. Fortes, C.S. Raghavendra, "Gracefully Degradable Processor Arrays", IEEE Trans. Comp., vol. C-34, n. 11, pp. 1033–1044 (Nov. 1985)Google Scholar
  10. [10]
    F.Lombardi, D.Sciuto, "Algorithms for Delay-bound Reconfiguration of Arrays", Proc. IFIP Workshop on Wafer-Scale Integration, Grenoble (March 1986)Google Scholar
  11. [11]
    A.L. Rosenberg, "The Diogenes approach to testable fault-tolerant VLSI processor arrays", IEEE Trans. Comp., vol. C-32, n. 10, pp. 902–910 (oct. 1983)Google Scholar
  12. [12]
    S.Hedlund, L.Snyder, "Wafer-scale integration of configurable highly parallel (CHiP) processor", Proc. International Conference Parallel Processing, pp. 262–264, IEEE (1982)Google Scholar
  13. [13]
    R.M. Mangir, A. Avizienis, "Fault-tolerant design for VLSI: effect of interconnection requirements on yield improvement of VLSI design", IEEE Trans. Comp., vol. C31, n. 7, pp. 609–615 (July 1982)Google Scholar
  14. [14]
    I. Koren, M.A Breuer, "On area and yield considerations for fault-tolerant VLSI processor arrays", IEEE Trans. con Comp., vol. C-33, n. 1, pp. 21–27 (Jan 1984)Google Scholar
  15. [15]
    M.G.Sami — R.Stefanelli, "Reconfigurable architectures for VLSI implementation", Proc. NCC 83, AFIPS, Los Angeles (May 1983)Google Scholar
  16. [16]
    M.G.Sami, R.Stefanelli, "Fault-tolerance of VLSI Processing Arrays: the time-redundancy approach", Proc. 1984 Real-Time Systems Symp., IEEE, Austin (Dec. 1984)Google Scholar
  17. [17]
    M.G. Sami, R. Stefanelli, "Fault-stealing: an approach to fault-tolerance of VLSI array structures", Proc. ICCAS 85, IEEE, Beijing (June 1985)Google Scholar
  18. [18]
    M.G.Sami — R.Stefanelli, "Reconfigurable architectures for VLSI processing arrays", Proceedings of the IEEE, Special issue of Fault-Tolerance for VLSI (May 1986)Google Scholar
  19. [19]
    M.G. Sami, R. Stefanelli, "Fault-tolerance and Functional Reconfiguration in VLSI arrays", Proc. ISCAS '86, vol. 2, pp. 643–648, San Jose (May 1986)Google Scholar
  20. [20]
    T. Leighton, C.E. Leiserson, "Wafer-Scale Integration of Systolic Arrays", IEEE Trans. on Comp., vol. C-34, n. 5, pp. 448–461 (May 1985)Google Scholar
  21. [21]
    R. Negrini, R. Stefanelli, "Algorithms for self-reconfiguration of wafer-scale regular arrays", Proc. ICCAS, IEEE, Beijing (1985)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1987

Authors and Affiliations

  • M. G. Sami
    • 1
  • N. Scarabottolo
    • 1
  1. 1.Department of ElectronicsPolitecnico di MilanoMilanoItaly

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