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Specification and properties of a cache coherence protocol model

  • C. Girault
  • C. Chatelain
  • S. Haddad
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 266)

Abstract

This paper describes a cache coherence protocol for an architecture composed of several processors, each with their own local cache, connected via a switching structure to a shared memory itself split into several modules managed by independent controllers. The protocol prevents processors from simultaneously modifying their respective copies and always provides a processor requiring a copy of a memory location with the most up-to-date version. A top down description and modeling of the protocol is given using Predicate/Transition nets. This modeling allows to formally describe the complex synchronizations of this protocol. Then invariants are directly obtained without unfolding the Predicate/Transition net. They are the basis for studying behavioral properties.

Keywords

Petri nets protocols specification verification cache coherence memory hierarchy multiprocessors 

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Copyright information

© Springer-Verlag Berlin Heidelberg 1987

Authors and Affiliations

  • C. Girault
    • 1
  • C. Chatelain
    • 1
  • S. Haddad
    • 1
  1. 1.Université Paris VI - C.N.R.S. (M.A.S.I. and PRC - C3/Algorithmes répartis)Paris Cedex 05

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