Multi-level simulator for VLSI

an overview
  • P. Mehring
  • E. Aposporidis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 258)


Simulation is a key element in modern and future digital circuit design. However, simulation becomes a bottleneck with increasing design complexity. There are mainly two ways to get out of this situation: reduction of the simulation load through multi-level simulation and acceleration of the simulation through exploitation of parallelism.

This paper deals with the development of a VLSI-Simulator which combines both approaches to achieve optimal performance. It is an informal overview of the work of AEG and its subcontractor Technische Universität Berlin carried out within ESPRIT Project 415.


Parallel Processing Digital Circuit Fault Simulation Algorithm Level Gate Level 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. /Abra83/.
    Abramovici, M. Levendel, Y.H. Menon, P.R. A Logic Simulation Machine; IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2 (1983), pp. 82–94Google Scholar
  2. /Albe86/.
    Albert, I. Müller-Schloer, C. Schwärtzel, H. CAD-Systeme für die industrielle Rechnerentwicklung; Informatik-Spektrum (1986) 9, pp. 14–28Google Scholar
  3. /Apos86/.
    Aposporidis, E. Daue, T. Mehring, P. Structure of a multi-level simulator exploiting maximal concurrency, ESPRIT 415, Doc. No. AEG 008-86, April 1986Google Scholar
  4. /Apos82/.
    Aposporidis, E. Jud, W. Logik-und Fehlersimulation kundenspezifischer Schaltungen; 10. Intern. Kongress Mikroelektronik, München, 9.-11. Nov. 1982, pp. 414–423Google Scholar
  5. /Blun77/.
    Blunden, D.F. Boyce, A.H. Taylor, G. Logic Simulation — Part 1; The Marconi Review, Vol. XL, No. 206, Third Quarter 1977, pp. 157–171Google Scholar
  6. /Jeff85/.
    Jefferson, D. Sowizral, H. Fast concurrent simulation using the time warp mechanism; SCS Multiconference, San Diego, Jan. 85, Part: Distributed Simulation, p. 63–69Google Scholar
  7. /Jorr86/.
    Jorrand, P. Term Rewriting as a Basis for the Design of a Functional and Parallel Programming Language; A case study: the Language FP2; in Fundamentals of Artificial Intelligence, LNCS 232, 1986Google Scholar
  8. /Lein81/.
    Leinwand, S.M. Process oriented Logic Simulation; IEEE, 18th Design Automation Conference, Paper 25.1, 1981, pp. 511–517Google Scholar
  9. /Lohn87/.
    Lohnert, F. Necessary Language Constructs for the Object-oriented Language with Respect to Logic Simulation ESPRIT 415, Doc. No. AEG 001-87, Febr. 1987Google Scholar
  10. /Scha87/.
    Schaefer, P. Schnoebelen, Ph. Specification of a pipelined event driven simulator using FP2; this volumeGoogle Scholar
  11. /Seit84/.
    Seitz, C.L. Concurrent VLSI Architectures; IEEE Transactions on Computers, Vol. c-33, No. 12, (December) 1984, pp. 1247–1265Google Scholar
  12. /Unge85/.
    Unger, B. Lomow, G. Andrews, K. A process oriented distributed simulation package; SCS Multiconference; Part: Distributed Simulation, January 1985, San Diego, S. 76–81Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1987

Authors and Affiliations

  • P. Mehring
    • 1
  • E. Aposporidis
    • 1
  1. 1.AEG Aktiengesellschaft, Berlin Research InstituteBerlin 51

Personalised recommendations