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Multi-level simulator for VLSI

an overview
  • P. Mehring
  • E. Aposporidis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 258)

Abstract

Simulation is a key element in modern and future digital circuit design. However, simulation becomes a bottleneck with increasing design complexity. There are mainly two ways to get out of this situation: reduction of the simulation load through multi-level simulation and acceleration of the simulation through exploitation of parallelism.

This paper deals with the development of a VLSI-Simulator which combines both approaches to achieve optimal performance. It is an informal overview of the work of AEG and its subcontractor Technische Universität Berlin carried out within ESPRIT Project 415.

Keywords

Parallel Processing Digital Circuit Fault Simulation Algorithm Level Gate Level 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1987

Authors and Affiliations

  • P. Mehring
    • 1
  • E. Aposporidis
    • 1
  1. 1.AEG Aktiengesellschaft, Berlin Research InstituteBerlin 51

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