Systolic array synthesis by static analysis of program dependencies

  • Sanjay V. Rajopadhye
  • Richard M. Fujimoto
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 258)


We present a technique for synthesizing systolic arrays which have non-uniform data flow governed by control signals. The starting point for the synthesis is a Recurrence Equation with Linear Depencencies (RELD) which is a generalization of the simple recurrences encountered in mathematics. A large class of programs, including all (single and multiple) nested-loop programs can be described by such recurrences. In this paper we extend some of our earlier work [17] in two principal directions. Firstly, we describe a transformation called multistage pipelining and show that it yields recurrences that have linear conditional expressions governing the computation. Secondly, we discuss how it is possible to automatically derive control signals that govern the data flow by applying the same pipelining transformations to these linear conditional expressions. The approach is illustrated by deriving the Guibas-Kung-Thompson architecture for optimum string parenthesization.


Basis Vector Null Space Recurrence Equation Systolic Array Conditional Expression 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1987

Authors and Affiliations

  • Sanjay V. Rajopadhye
    • 1
  • Richard M. Fujimoto
    • 2
  1. 1.Computer and Info. Sci. Dept.University of OregonEugene
  2. 2.Computer Science DepartmentUniversity of UtahSalt Lake City

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