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Hardware memory management for large knowledge bases

  • S. H. Lavington
  • M. Standring
  • Y. J. Jiang
  • C. J. Wang
  • M. E. Waite
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 258)

Abstract

Large knowledge bases form an important applications area for parallel architectures. The special problems of this domain concern the movement and protection of large amounts of complex data in a hierarchy of storage devices and processing elements, in a manner which is sympathetic to the logical structure of the information. This structure is a reflection of the underlying knowledge representation formalism. An analysis of candidate formalisms leads to the specification of a memory architecture for large knowledge bases. The particular problems of paging are studied, and a scheme for semantic caching is proposed. The design of a fast cache employing highly-parallel pattern-directed searching is described. The performance of this cache in a multi-level memory hierarchy is given.

Keywords

Transitive Closure Semantic Network Memory Management Boltzmann Machine Wild Card 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1987

Authors and Affiliations

  • S. H. Lavington
    • 1
  • M. Standring
    • 2
  • Y. J. Jiang
    • 1
  • C. J. Wang
    • 2
  • M. E. Waite
    • 1
  1. 1.Dept. of Computer ScienceUniversity of EssexColchester
  2. 2.Dept. of Computer ScienceUniversity of ManchesterManchester

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