# A simple implementation of Warshall's algorithm on a vlsi chip

Algorithmic And Network Considerations

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## Abstract

The key step in the Warshall's well known algorithm for transitive closure of a graph [1] involves a recurrence equation of the following type: where f

$$f_k \left( {i,{\text{ }}j} \right) = f_{k - 1} \left( {i,{\text{ }}j} \right) + f_{k - 1} \left( {i,{\text{ }}k} \right).f_{k - 1} \left( {k,{\text{ }}j} \right),{\text{ }}1 \leqslant i,{\text{ }}j,{\text{ }}k \leqq n$$

(1)

_{ø}(i,j) ist the (i,j)^{th}element of the adjacency matrix of the given graph and f_{n}(i,j) the final required result.Van Scoy [2] proposed a scheme to implement Warshall's algorithm in O(n) time using n which occurs quite frequently as a key step in many graph theoretic algorithms [3].

^{2}processors arranged in the form of a square with ‘Wraparound’ connections. But the algorithm and its proof of correctness are quite complicated with several subcases (The analysis of the content of ‘position’ register alone extends to 29 cases). Moreover, it is difficult to conceive of a design to solve a generalised recurrence equation of the type$$f_k \left( {i,{\text{ }}j} \right) = g\left( {f_{k - 1} \left( {i,{\text{ }}j} \right),{\text{ }}f_{k - 1} \left( {i,{\text{ }}k} \right),{\text{ }}f_{k - 1} \left( {k,{\text{ }}j} \right)} \right)$$

In this paper we shall describe a new scheme with full details of the implementation, which is quite simple and suitable for VLSI chip fabrication. We shall also outline how the algorithm can be implemented even without wraparound connections. In both the cases the time taken to solve the problem is O(n).

## Keywords

Transitive Closure Shift Vertical Shift Horizontal Horizontal Path Input Selection## Preview

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## References

- [1]Warshall, ‘A Theorem on Boolean Matrices", J. ACM, Vol. 9, 1962, 11–12.Google Scholar
- [2]Van Scoy, ‘Parallel recognition of classes of Graphs', IEEE Trans. on Computers, Vol. C-29, 1980, 563–570.Google Scholar
- [3]Atallah and Kosaraju, ‘Graph Problems on a Mesh-connected Processor Array', J. ACM, Vol. 31, 1984, 649–667.Google Scholar

## Copyright information

© Springer-Verlag Berlin Heidelberg 1987