On synthesizing systolic arrays from Recurrence Equations with Linear Dependencies

  • Sanjay V. Rajopadhye
  • S. Purushothaman
  • Richard M. Fujimoto
Session 8 Parallel Algorithms
Part of the Lecture Notes in Computer Science book series (LNCS, volume 241)


We present a technique for synthesizing systolic architectures from Recurrence Equations. A class of such equations (Recurrence Equations with Linear Dependencies) is defined and the problem of mapping such equations onto a two dimensional architecture is studied. We show that such a mapping is provided by means of a linear allocation and timing function. An important result is that under such a mapping the dependencies remain linear. After obtaining a two-dimensional architecture by applying such a mapping, a systolic array can be derived if the communication can be spatially and temporally localized. We show that a simple test consisting of finding the zeroes of a matrix is sufficient to determine whether this localization can be achieved by pipelining and give a construction that generates the array when such a pipelining is possible. The technique is illustrated by automatically deriving a well known systolic array for factoring a band matrix into lower and upper triangular factors.


Timing Function Dependency Structure Recurrence Equation Systolic Array Initial Specification 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Brent, R. P. and Kung, H. T. Systolic VLSI Arrays for Linear-Time GCD Computation. VLSI 83, August, 1983, pp. 145–154.Google Scholar
  2. 2.
    Cappello, P. R. and Steiglitz, K. "Unifying VLSI Designs with Linear Transformations of Space-Time". Advances in Computing Research (1984), 23–65.Google Scholar
  3. 3.
    Chen, M. C. Space-Time Algorithms: Semantics and Methodology. Ph.D. Th., California Institute of Technology, Pasadena, Ca, May 1983.Google Scholar
  4. 4.
    Chen, M. C. Synthesizing systolic designs. YALEU/Dept. Of Computer Science/RR-374, Yale University, March, 1985.Google Scholar
  5. 5.
    Chen, M. C. A Parallel Language and its Compilation to Multiprocessor Machines or VLSI. Principles of Programming Languages, ACM, 1986.Google Scholar
  6. 6.
    Delosme, J. M. and Ipsen I. C. F. An illustration of a methodology for the construction of efficient systolic architectures in VLSI. International Symposium on VLSI Technology, Systems and Applications, Taipei, Taiwan, 1985, pp. 268–273.Google Scholar
  7. 7.
    Guibas, L., Kung, H. T. and Thompson, C. D. Direct VLSI Implementation of Combinatorial Algorithms. Proc. Conference on Very Large Scale Integration: Architecture, Design and Fabrication, January, 1979, pp. 509–525.Google Scholar
  8. 8.
    Johnsson, S. L., Weiser, U. C., Cohen, D. and Davis, A. L. Towards a Formal Treatment of VLSI Arrays. Proceedings of the second Caltech Conference on VLSI, January, 1981, pp. 375–398.Google Scholar
  9. 9.
    Karp, R. M., Miller, R. E. and Winograd, S. "The Organization of Computations for Uniform Recurrence Equations". JACM 14, 3 (July 1967), 563–590.Google Scholar
  10. 10.
    Kung, H. T. Let's design algorithms for VLSI. Proc. Caltech Conference on VLSI, January, 1979.Google Scholar
  11. 11.
    Kung, H. T. and Leiserson, C. E. Algorithms for VLSI Processor Arrays. In Mead, C. and Conway, L., Ed., Introduction to VLSI Systems, Addison-Wesley, Reading, Ma, 1980, Chap. 8.3, pp. 271–292.Google Scholar
  12. 12.
    Kung, H. T. "Why Systolic Architectures", Computer 15, 1 (January 1982), 37–46.Google Scholar
  13. 13.
    Lam, M. S. and Mostow, J. A. "A Transformational Model of VLSI Systolic Design". IEEE Computer 18 (February 1985), 42–52.Google Scholar
  14. 14.
    Leiserson, C. E. and Saxe, J. B. "Optimizing Synchronous Systems". Journal of VLSI and Computer Systems 1 (1983), 41–68.Google Scholar
  15. 15.
    Li, G. J. and Wah, B. W. "Design of Optimal Systolic Arrays". IEEE Transactions on Computers C-35, 1 (1985), 66–77.Google Scholar
  16. 16.
    Melhem, R. G. and Rheinboldt, Werner C. "A Mathematical Model for the Verification of Systolic Networks", SIAM Journal of Computing 13, 3 (August 1984), 541–565.Google Scholar
  17. 17.
    Miranker, W. L. and Winkler, A. "Space-Time Representation of Computational Structures". Computing 32 (1984), 93–114.Google Scholar
  18. 18.
    Moldovan, D. I. "On the Design of Algorithms for VLSI Systolic Arrays". Proceedings of the IEEE 71, 1 (January 1983), 113–120.Google Scholar
  19. 19.
    O'Keefe, M. T. and Fortes, J. A. B. A Comparative Study of two Systematic Design Methodologies for Systolic Arrays. International Conference on Parallel Processing, IEEE, St. Charles, Ill, August, 1986.Google Scholar
  20. 20.
    Quinton, P. The Systematic Design of Systolic Arrays. 216, Institut National de Recherche en Informatique et en Automatique [INRIA], July 1983.Google Scholar
  21. 21.
    Rajopadhye, S. V. and Fujimoto, R. M. Systolic Array Synthesis by Static Analysis of Program Dependencies. UUCS-86-0011, University of Utah, Computer Science Department, August, 1986. Submitted for Publication.Google Scholar
  22. 22.
    Rajopadhye, S. V. Synthesis, Otimization and Verification of Systolic Architectures. Ph.D. Th., University of Utah, Salt Lake City, Utah 84112, September 1986.Google Scholar
  23. 23.
    Ramakrishnan, I. V., Fussell, D. S. and Silberschatz, A. "Mapping Homogeneous Graphs on Linear Arrays". IEEE Transactions on Computers C-35 (March 1985), 189–209.Google Scholar
  24. 24.
    Rockafellar, R. T., Corwex Analysis. Princeton University Press, 1970.Google Scholar
  25. 25.
    Weiser, U. C. and Davis, A. L. A Wavefront Notational Tool for VLSI Array Design. VLSI Systems and Computations, Carnegie Mellon University, October, 1981, pp. 226–234.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • Sanjay V. Rajopadhye
    • 1
  • S. Purushothaman
    • 2
  • Richard M. Fujimoto
    • 3
  1. 1.Computer and Info. Sc. Dept.University of OregonEugeneUSA
  2. 2.Computer Science Dept.Penn State UniversityState CollegeUSA
  3. 3.Computer Science Dept.University of UtahSalt Lake CityUSA

Personalised recommendations