Lisa: A parallel processing architecture

  • G. M. Megson
  • D. J. Evans
Architectural Aspects (Session 5.1)
Part of the Lecture Notes in Computer Science book series (LNCS, volume 237)


The purpose of this paper is two-fold. Firstly, it introduces and develops the ideas of the Linear Instruction Systolic Array (LISA), and shows that it can simulate MIMD, SIMD and Systolic Wavefront Processor Algorithms involving nobacktracking.

Secondly, we show that it can be used to develop a powerful Parallel Architecture based on LISA chips, which should be expandable and area efficient.

As a subsidiary argument we can also demonstrate that there is real evidence for the role of Systolic Computation particularly pipelining in the development of parallel computations.


Program Transformation Processor Array Linear Systolic Array Selector Information Systolic Implementation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • G. M. Megson
    • 1
  • D. J. Evans
    • 1
  1. 1.Department of Computer StudiesLoughborough University of TechnologyLoughboroughU.K.

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