Hierarchical array processor system (HAP)

  • Shigeharu Momoi
  • Shigeo Shimada
  • Masamitsu Kobayashi
  • Tsutomu Ishikawa
Hardware Aspects & Nonnumerical Algorithms (Session 4.2)
Part of the Lecture Notes in Computer Science book series (LNCS, volume 237)


A MIMD type highly parallel processor comprising 4096 processing elements (PEs) with a nearest neighbor mesh connection is studied. The system realizes more than 100MB/S initial data transfer capability by multi-layering PE arrays, transmitting data from each upper layer PE to dependent lower layer PEs simultaneously. This configuration reduces the maximum internode distance and the inter-PE data transfer delay by relaying inter-PE data via upper layer PEs. High speed inter-PE synchronizations, for instance, synchronization of all PEs and local synchronization within any layer, have been realized (less than one microsecond for all PEs). A small scale system with 256 PEs is now under fabrication. Each PE consists of a 16-bit micro-processor, DRAMs and two newly developed types of LSIs. The size of a PE is 9cm × 6cm × 3cm.


Data Transfer Memory Access Processing Element Parallel Processor Processing Element Array 


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Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • Shigeharu Momoi
    • 1
  • Shigeo Shimada
    • 1
  • Masamitsu Kobayashi
    • 1
  • Tsutomu Ishikawa
    • 1
  1. 1.NIT Electrical Communications LaboratoriesTokyoJapan

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