Information processing with associative processors

  • Hans-Albert Schneider
  • Werner Dilger
Architectural Aspects (Session 3.1)
Part of the Lecture Notes in Computer Science book series (LNCS, volume 237)


Associative processors keep their data in content addressable memories (CAMs) accessing them by content, not address. Our interest concentrates on how associative processors can be used for inference processes.

We have developed the model of an associative processor based on the Deduction Plan theorem proving method. Our approach also includes a unification algorithm which provides information about all causes of unification conflicts (if any) and allows simple backtracking of the unification graph.


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6. References

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    C.-L. Chang, R. C.-T. Lee: Symbolic Logic and Mechanical Theorem Proving. Academic Press, New York 1973Google Scholar
  2. [2]
    W. Dilger, A. Janson: Unifikationsgraphen für intelligentes Backtracking in Deduktionssystemen. Proc. GWAI-83, Informatik-Fachberichte 76, Springer Verlag Berlin 1983, 189–196.Google Scholar
  3. [3]
    S. Matwin, T. Pietrzykowski: Intelligent Backtracking in Plan-Based Deduction. IEEE Trans. on Pattern Analysis and Machine Intelligence, vol. PAMI-7 (1985), 682–692.Google Scholar
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    B. Parhami: Associative Memories and Processors. An Overview and Selected Bibliography. Proc. IEEE 61 (1973), 722–730.Google Scholar
  5. [5]
    R.E. Shostak: Refutation graphs. Artificial Intelligence, vol. 7 (1976), 51–64.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • Hans-Albert Schneider
    • 1
  • Werner Dilger
    • 2
  1. 1.Universität Kaiserslautern Fachbereich InformatikKaiserslautern
  2. 2.FhG-IITBKarlsruhe

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