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Diogenes, circa 1986 Ψαχνω για ενα τιμιo ανϑρoπo

  • Arnold L. Rosenberg
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 227)

Abstract

The DIOGENES methodology produces designs for fault-tolerant VLSI processor arrays in two stages: First, the desired array is viewed as an undirected graph and is embedded in a book; then, the book embedding is converted to an efficient fault-tolerant layout of the array. We survey here work on both stages of the methodology, highlighting recent progress and pointing out remaining challenges.

Keywords

Optimal Assignment Processor Array Outerplanar Graph Vertex Graph Partial Assignment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • Arnold L. Rosenberg
    • 1
  1. 1.Dept. of Computer ScienceDuke UniversityDurham

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