Optimal tradeoffs for addition on systolic arrays

Extended abstract
  • Alok Aggarwal
  • J. Lawrence Carter
  • S. Rao Kosaraju
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 227)


The complexity of adding two n-bit numbers on a two-dimensional systolic array is investigated. We consider different constraints on the systolic array, including:
  • —whether or not the input and output ports lie on the periphery of the array

  • —whether or not the i/o schedule is where-determinate

  • —constraints that are placed on the arrival and departure times of inputs and outputs

For all combinations of the above constraints, we obtain optimal tradeoffs among the resources of area, pipeline delay, and worst-case time. It turns out that there is a subtle interplay among the constraints and some of our results seem counter intuitive. For instance, we show that allowing more significant bits to arrive earlier than less significant bits can speed up addition by a factor of log n. On the other hand, we show that some known results such as Chazelle and Monier's bounds for arrays that have i/o on the perimeter, also hold in less constrained models. Some of our results are obtained by modifying known techniques, whereas, new proof methods are required for other results.


Cellular Automaton Time Instant Systolic Array Parallel Array Optimal Tradeoff 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • Alok Aggarwal
    • 1
  • J. Lawrence Carter
    • 1
  • S. Rao Kosaraju
    • 2
  1. 1.IBM T. J. Watson CenterYorktown Heights
  2. 2.Department of Electrical Engineering and Computer ScienceThe Johns Hopkins UniversityBaltimore

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