Abstract
The complexity of adding two n-bit numbers on a two-dimensional systolic array is investigated. We consider different constraints on the systolic array, including:
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—whether or not the input and output ports lie on the periphery of the array
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—whether or not the i/o schedule is where-determinate
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—constraints that are placed on the arrival and departure times of inputs and outputs
For all combinations of the above constraints, we obtain optimal tradeoffs among the resources of area, pipeline delay, and worst-case time. It turns out that there is a subtle interplay among the constraints and some of our results seem counter intuitive. For instance, we show that allowing more significant bits to arrive earlier than less significant bits can speed up addition by a factor of log n. On the other hand, we show that some known results such as Chazelle and Monier's bounds for arrays that have i/o on the perimeter, also hold in less constrained models. Some of our results are obtained by modifying known techniques, whereas, new proof methods are required for other results.
Supported by NSF Grant No. DCR 850-6361.
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References
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© 1986 Springer-Verlag Berlin Heidelberg
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Aggarwal, A., Carter, J.L., Kosaraju, S.R. (1986). Optimal tradeoffs for addition on systolic arrays. In: Makedon, F., Mehlhorn, K., Papatheodorou, T., Spirakis, P. (eds) VLSI Algorithms and Architectures. AWOC 1986. Lecture Notes in Computer Science, vol 227. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-16766-8_6
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DOI: https://doi.org/10.1007/3-540-16766-8_6
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