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Exploiting hierarchy in VLSI design

  • T. Lengauer
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 227)

Abstract

Recently design systems have been developed, that consider hierarchical circuit design not only as a means for more concise circuit specification but as a basis of more efficient design analysis and optimization. Hierarchical tools are most abundant in the area of artwork analysis, but they also occur in other areas such as compaction, layout, and simulation. In this paper we give an overview of approaches to hierarchical circuit processing. Hereby, we mention specific tools as well as algorithmic and conceptual work that may point to further hierarchical tool development.

Keywords

Minimum Span Tree Hierarchical Processing Boolean Circuit Designer Hierarchy Hierarchical Description 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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6. References

  1. [AO 82]
    Arnold, M.H./Ousterhout, J.K.: Lyra: A new approach to geometric design rule checking. Proc. 19th Design Automation Conference (1982), 530–536Google Scholar
  2. [BB 86]
    Brayton, R.K./Brenner, N.L./Chen, C.L./DeMicheli, G./McMullen, C.T./Otten, R.H.J.M.: The YORKTOWN Silicon Compiler. Proc. of International Symposium on Circuits and Systems (ISCAS '85) (1985)Google Scholar
  3. [BK 83]
    Breuer, M.A./Kumar, A.: A methodology for custom VLSI layout. IEEE trans. Circuits and Systems. CAS-30,6 (1983), 358–364Google Scholar
  4. [BO 83]
    Bentley, J.L./Ottmann, T./Widmayer, P.: The complexity of manipulating hierarchically defined sets of rectangles. In: Advances in Computing Research (JAI Press Inc.) 1 (1983), 127–158Google Scholar
  5. [Br 84]
    Bryant, R.E.: A switch-level model and simulator for MOS digital systems. IEEE Trans. Comput. C-33,2 (1984), 160–177Google Scholar
  6. [CAP]
    Rammig, F.J.: Mixed-level modelling and simulation of VLSI systems. Advances in CAD for VLSI, Vol. II (E. Hörbst, ed.), North-Holland (1986)Google Scholar
  7. [CH 80]
    Chao, S./Huang, Y./Yan, L.M.: A hierarchical approach for layout versus circuit consistency check. Proc. 17th Design Automation Conference (1980), 269–276Google Scholar
  8. [CM 83]
    Chen, M.C./Mead, C.A.: A hierarchical simulator based on formal semantics. Proc. 3rd Caltech VLSI Conference (R.E. Bryant, ed.) (1983), 207–224Google Scholar
  9. [ED 85]
    Entenmann, G./Daniel, S.W.: A fully automatic hierarchical compactor. Proc. 22nd Design Automation Conference (1985), 69–75Google Scholar
  10. [GG 85]
    Gabow, H.N./Galil, Z./Spencer, T./Tarjan, R.E.: Efficient algorithms for finding minimum spanning trees in undirected and directed graphs. Typescript (1985). To appear in COMBINATORIKAGoogle Scholar
  11. [GH 83]
    Gupta, A./Hon, R.W.: HEXT: A hierarchical circuit extractor. Journal of VLSI and Computer Systems 1, 1 (1983), 23–39Google Scholar
  12. [HILL]
    Lengauer, T./Mehlhorn, K.: The HILL system: A design environment for the hierarchical specifcation, compaction, and simulation of integrated circuit layouts. Proc. MIT-Conference on Advanced Research in VLSI (P. Penfield Jr. ed.), Artech House Company (1984), 139–148Google Scholar
  13. [HILO]
    Flake, P.L./Moorby, P.R./Musgrave, G.: HILO Mark 2, Hardware description language. Proc. of 5th Conference on Computer Hardware Description Languages and Their Applications (M. Breuer, K. Hartenstein, eds.), North Holland (1981), 95–108Google Scholar
  14. [Ho 83]
    Hon, R.W.: The hierarchical analysis of VLSI designs. Ph.D. Thesis, Computer Science Dep., Carnegie-Mellon University, Pittsburgh, PA (1983)Google Scholar
  15. [HS 84]
    Huang, M.A./Steiglitz, K.: A hierarchical compaction algorithm with low page fault complexity. Proc. of the MIT-Conference on Advanced Research in VLSI (P. Penfield Jr., ed.) (1984), 203–212Google Scholar
  16. [Jo 82]
    Johnson, S.C.: Hierarchical design validation based on rectangles. Proc. MIT Conference on Advanced Research in VLSI (P. Penfield Jr., ed.) (1982), 97–100Google Scholar
  17. [KC 85]
    Katz, R.H./Chang, E./Bhateja, R.: Version modeling concepts for computer-aided design databases. Report No. UCB/CSD86/270, University of California, Berkeley, CA (1985)Google Scholar
  18. [Ki 84]
    Kingsley, C.: A hierarchical error-tolerant compactor. Proc. 21st Design Automation Conference (1984), 126–132Google Scholar
  19. [KN 82]
    Keller, K.H./Newton, A.R./Ellis, S.: A symbolic design system for integrated circuits. Proc. 19th Design Automation Conference (1982), 460–466Google Scholar
  20. [Le 82]
    Lengauer, T.: The complexity of compacting hierarchically specified layouts of integrated circuits. Proc. of 23rd IEEE-FOCS (1982), 358–368Google Scholar
  21. [Le 84]
    Lengauer, T.: Hierarchical graph algorithms. TR-SFB 124, No. 15, FB 10, Universität des Saarlandes, Saarbrücken, West-Germany (1984)Google Scholar
  22. [Le 85]
    Lengauer, T.: Efficient solution of biconnectivity problems on hierarchically defined graphs. Proc. of the WG '85 (H. Noltemeier, ed.), Trauner Verlag (1985), 201–216Google Scholar
  23. [Le 86a]
    Lengauer, T.: Efficient algorithms for finding minimum spanning forests of hierarchically defined graphs. Proc. of STACS 86, Springer Lecture Notes in Computer Science No. 216 (1986), 153–170Google Scholar
  24. [Le 86b]
    Lengauer, T.: Hierarchical planarity testing algorithms. Proc. of ICALP 86, Springer Lecture Notes in Computer Science (1986)Google Scholar
  25. [MC 80]
    Mead, C./Conway, L.: Introduction of VLSI systems. Addison-Wesley (1980)Google Scholar
  26. [NF 82]
    Newell, M.E./Fitzpatrick, D.T.: Exploitation of hierarchy in analyses of integrated circuit artwork. IEEE Trans. on CAD-ICAS, Vol. CAD-1,4 (1982), 192–200Google Scholar
  27. [Ro 80]
    Rowson, J.A.: Understanding hierarchical design. Ph.D. Thesis, Computer Science Dep., California Institute of Technology, Pasadena, CA (1980)Google Scholar
  28. [Sa 70]
    Savitch, W.J.: Relationship between non-deterministic and deterministic tape complexities. JCSS 4,2 (1970), 177–192Google Scholar
  29. [Sc 84]
    Scheffer, L.K.: The use of strict hierarchy for verification of integrated circuits. Ph.D. Thesis, Stanford University, Stanford, CA (1984)Google Scholar
  30. [Sh 85]
    Shand, M.A.: Hierarchical VLSI artwork analysis. Proc. of VLSI 85 (1985), 415–424Google Scholar
  31. [SS 86]
    Scheffer, L.K./Soetarman, R.: Hierarchical analysis of IC artwork with user-defined rules. IEEE Design & Test (Feb. 1986), 66–74Google Scholar
  32. [STYX]
    Jerraya, A./Rosier, E./Rougeaux, F.R./Courtois, B.: A hierarchical symbolic design layout tool: STYX. Proc. of VLSI 85 (1985), 329–337Google Scholar
  33. [TH 83]
    Tarolli, G.M./Herman, W.J.: Hierarchical circuit extraction with detailed parasitic capacitance. Proc. 20th Design Automation Conference (1983), 337–345Google Scholar
  34. [TE 85]
    Tygar, J.D./Ellikson, R.: Efficient netlist comparison using hierarchy and randomization. Proc. 22nd Design Automation Conference (1985), 702–708Google Scholar
  35. [TO 83]
    Taylor, G.S./Ousterhout, J.K.: Magic's incremental design rule checker. Proc. 21st Design Automation Conference (1984), 160–165Google Scholar
  36. [U 84]
    Ullmann, J.D.: Computational aspects of VLSI. Computer Science Press (1984)Google Scholar
  37. [VIVID]
    Rosenberg, J.: A vertically integrated VLSI design environment. Proc. 20th Design Automation Conference (1983), 31–35Google Scholar
  38. [VR 85]
    van Vlierberghe, S./Rijmenants, J./Heyns, W.: Symbolic hierarchical artwork generation system. Proc. 22nd Design Automation Conference (1985), 789–793Google Scholar
  39. [Wa 85]
    Wagner, T.J.: Hierarchical layout verification. Proc. 21st Design Automation Conference (1984), 484–489Google Scholar
  40. [Wh 81]
    Whitney, T.: A hierarchical design rule checking algorithm. Lambda (first quarter 1981)Google Scholar
  41. [Wh 85]
    Whitney, T.E.: Hierarchical composition of VLSI circuits. Ph.D. Thesis, Computer Science Dep., California Institute of Technology, Pasadena, CA (1985)Google Scholar
  42. [Wo 85]
    Wong, Y.: Hierarchical circuit verification. Proc. 22nd Design Aut. Conference (1985), 695–701Google Scholar
  43. [Zi 86]
    Zimmermann, G.: Top-down design of digital systems. Advances in CAD for VLSI, Vol. II (E. Hörbst, ed.), North Holland (1986)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • T. Lengauer
    • 1
  1. 1.Fachbereich 17Universität-GH PaderbornPaderbornWest-Germany

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