A high-performance single-chip vlsi signal processor architecture

  • Nick Kanopoulos
  • Peter N. Marinos
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 227)


The single-chip, high-performance signal processor design described in this paper departs from existing processor designs both in the way it is organized and the manner in which it performs computations. Major emphasis is placed on the exploitation of parallelism and pipelining inherently present in signal processing functions, and on novel processing architecture that allows mapping of high-level computations, such as Fast-Fourier-Transforms (FFT), directly into hardware. The single-chip design is based on a 2μ-CMOS technology, utilizes bit-serial arithmetic and is externally provided with appropriately organized first-in/first-out (FIFO) memory. The processor is suitable for use in real-time situations such as radar, sonar, and seismic data processing.


Control Word Constant False Alarm Rate Seismic Data Processing Processor Design Radar Signal Processing 
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Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • Nick Kanopoulos
    • 1
  • Peter N. Marinos
    • 2
  1. 1.Digital Systems ResearchResearch Triangle InstituteResearch Triangle Park
  2. 2.Dept. of Electrical EngineeringDuke UniversityDurham

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