Advertisement

A high-performance single-chip vlsi signal processor architecture

  • Nick Kanopoulos
  • Peter N. Marinos
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 227)

Abstract

The single-chip, high-performance signal processor design described in this paper departs from existing processor designs both in the way it is organized and the manner in which it performs computations. Major emphasis is placed on the exploitation of parallelism and pipelining inherently present in signal processing functions, and on novel processing architecture that allows mapping of high-level computations, such as Fast-Fourier-Transforms (FFT), directly into hardware. The single-chip design is based on a 2μ-CMOS technology, utilizes bit-serial arithmetic and is externally provided with appropriately organized first-in/first-out (FIFO) memory. The processor is suitable for use in real-time situations such as radar, sonar, and seismic data processing.

Keywords

Control Word Constant False Alarm Rate Seismic Data Processing Processor Design Radar Signal Processing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    J. Hennessey et al, "A VLSI Processor Architecture," Comp. Syst. Laboratory, Technical Report No. 223, Stanford Univ., (Nov. 1981).Google Scholar
  2. 2.
    W. Bauer, "The NEC PD7720/SPI and an Application Development in Speech Digitation," Proceedings WESCON — 82, 34/4, (1982).Google Scholar
  3. 3.
    P. P. Reusens, R. W. Linderman, W. K. Ku, "CUSP: A Custom VLSI Processor for Digital Signal Processing Based on the FFT," Proceedings, ICCD, pp. 757–760, (1983).Google Scholar
  4. 4.
    H. E. Tsou, A. S. Hamori, B. L. Troutman, "A High Speed Multi-Purpose VLSI Digital Processor," Proceedings, ICCD, pp. 141–144, (1983).Google Scholar
  5. 5.
    B. Arambepola, "Algorithm and a New Processor Architecture for Computing the DFT," Proceedings, Int'l. Conf. on Acoustics, Speech and Signal Processing, pp. 451–454, (1983).Google Scholar
  6. 6.
    D. Gwyn, P. Edwards, "The AMI 52811 Advanced Signal Processing Peripheral," Proceedings, WESCON — 82, 34/1, (1982).Google Scholar
  7. 7.
    M. Yano, K. Inoke, T. Senba, "An LSI Digital Signal Processor," Proceedings, Int'l. Conf. on Acoustics, Speech and Signal Processing, pp. 1073–1076, (1982).Google Scholar
  8. 8.
    B. Huston, "CMOS Single-Chip Family Enhanced with an EPROM Version," Proceedings, WESCON — 82, 5B-L, (1982).Google Scholar
  9. 9.
    T. Tsuda et al, "CMOS LSI DSP and its Applications to Voice Band Signals," Proceedings Int'l. Conf. on Acoustics, Speech and Signal Processors, pp. 955–958, (1983).Google Scholar
  10. 10.
    J. D. Grimm, G. L. Bair, "Radar Signal Processing Development for Application of VHSI," Proceedings, NAECON-79, pp. 796-805, (1979).Google Scholar
  11. 11.
    E. O. Brigham, The Fast Fourter Transform, Prentice Hall, Englewood Cliffs, (1974).Google Scholar
  12. 12.
    N. Kanopoulos, "A Single-chip VLSI Architecture for Radar Signal Processing," Ph.D. Dissertation, Duke University, (1984).Google Scholar
  13. [13.]
    N. Kanopoulos, "Design and Implementation of a 40-by-20 FIFO Memory for a VLSI System," Proceedings, MELECON-83, pp. B304-B306, (1983).Google Scholar
  14. 14.
    G. Culler, E. Greenwood, D. Harrison, "A High Performance VLSI CMOS Arithmetic Processor Chip," Proceedings, Int'l. Conf. on Acoustics, Speech and Signal Processing, pp. 1053–1056, (1982).Google Scholar
  15. 15.
    R. E. Holm, "New Approaches to DSP Expand Capabilities of Single-chip Processors," Proceedings, WESCON-82, 34/5, (1982).Google Scholar
  16. 16.
    Advanced Micro Devices, "Digital Signal/Array Processing Products," New Product Information, (1983).Google Scholar
  17. 17.
    B. L. Troutman et al, "A 2μ CMOS/LSI 32-Point FFT Processor," Proceedings, Int'l. Solid State Circuits Conf., pp. 26–27, (1982).Google Scholar
  18. 18.
    Texas Instruments, "TMS 320 16/32 Bit Single-chip Processor," Specification Manual, (1982).Google Scholar
  19. 19.
    F. E. Nathanson, Radar Design Principles, McGraw-Hill, New York, (1968).Google Scholar
  20. 20.
    E. Brookner, "Trends in Radar Signal Processing," Microwave Journal, pp. 19–30, (October 1982).Google Scholar
  21. 21.
    E. Brookner, "Developments in Digital Radar Processing," Journal reprints of Raytheon Comp., pp. 7–17, (March 1983).Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • Nick Kanopoulos
    • 1
  • Peter N. Marinos
    • 2
  1. 1.Digital Systems ResearchResearch Triangle InstituteResearch Triangle Park
  2. 2.Dept. of Electrical EngineeringDuke UniversityDurham

Personalised recommendations