Efficient modular design of TSC checkers for m-out-of-2m codes

  • A. M. Paschalis
  • D. Nikolos
  • C. Halatsis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 227)


A new design method of TSC m-out-of-2m code checkers is presented. The design is composed basically of two full-adder/half-adder trees, each summing-up the one's of m input lines, and a k-variable 2-pair two-rail code tree that compares the outputs of the two adder trees. The only modules used are full-adders, half-adders and two-rail T2. This method is well suited for VLSI MOS implementation and compared to previous methods it results in significant circuit cost reduction and smaller test set, without sacrificing performance. At the same time the proposed design has all added advantages of a modular design.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • A. M. Paschalis
    • 1
  • D. Nikolos
    • 2
  • C. Halatsis
    • 3
  1. 1.Dept. of ComputersNRC "Democritos" Aghia ParaskeviAthensGreece
  2. 2.Computers LaboratoryUniversity of AthensAthensGreece
  3. 3.Digital Systems and Computers LaboratoryUniv. of ThessalonikiThessalonikiGreece

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