Linear algorithms for two CMOS layout problems

  • Rolf Müller
  • Thomas Lengauer
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 227)


[UC,BNR] formulate a linear layout problem for static CMOS gates and give partial solutions of the problem. [O] reformulates the problem in two ways for dynamic CMOS cells and gives partial solutions. We give complete solutions to both problems formulated by [O] by giving linear algorithms.


Decomposition Tree Layout Problem Simple Path Linear Time Algorithm Linear Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [BB]
    Brayton, R.K./Brenner, N.L./Chen, C.L./DeMicheli, G./ McMullen, C.T. & Otten, R.H.J.M.: The Yorktown Silicon Compiler. ISCAS '85, Kyoto, Japan, June 1985Google Scholar
  2. [BC]
    Brayton, R.K./Chen, C.L./Otten, R.H.J.M. & Yamour, Y.Y.: Automatic Implementation Of Switching Functions As Dynamic CMOS Circuits. CICC 1984Google Scholar
  3. [BNR]
    Bruss, A./Nair, R. & Reif, J.: Linear Time Algorithms For Optimal CMOS Layout. IBM, Thomas J. Watson Research Center, Yorktown Heights, New York, Research Report, Dec. 1983Google Scholar
  4. [E]
    Even, S.: Graph Algorithms. Pitman, London 1979Google Scholar
  5. [I]
    Ibaraki, T. & Muroga, S.: Minimization of Switching Networks Using Negative Functions. Department of Computer Science, University of Illinois, Urbana, Ill., Report 309, February 1969Google Scholar
  6. [M]
    Muroga, S: Logic Design and Switching Theory. John Wiley, New York 1979Google Scholar
  7. [MC]
    Mead, C. & Conway, L.: Introduction To VLSI-Systems. Addison Wesley 1980Google Scholar
  8. [Mü]
    Müller, R.: Lineare Algorithmen für ein Layoutproblem für CMOS-Gatter. Diploma thesis, University of Paderborn, Paderborn, West Germany, January 1986Google Scholar
  9. [N]
    Nakamura, K./Tokura, N. & Kasani, T.: Minimal Negative Gate Networks. IEEE Trans. Comput., Jan 5–11, 1972Google Scholar
  10. [O]
    Otten, R.H.J.M.: Layout Compilation From A Functional Description. Overhead slides of a talk at IBM Europe Institute, Lech, Austria 1985Google Scholar
  11. [O2]
    Otten, R.H.J.M.: personal communication, June 1985Google Scholar
  12. [UC]
    Uehara, T. & van Cleemput, W.M.: Optimal Layout of Functional Arrays. IEEE Trans. Comput., pp 305–312, May 1981Google Scholar
  13. [V]
    Valdes, J.: Parsing Flowcharts And Series-Parallel Graphs. Ph.D. dissertation, Department Of Computer Science, Stanford University, Dec. 1978Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • Rolf Müller
    • 1
  • Thomas Lengauer
    • 1
  1. 1.Fachbereich 17University of PaderbornPaderbornWest Germany

Personalised recommendations