Correspondence between ternary simulation and binary race analysis in gate networks
Ternary simulation techniques provide efficient methods for the analysis of the behavior of VLSI circuits. However, the results of ternary simulation have not been completely characterized. In this paper we outline the proof of the Brzozowski-Yoeli conjecture (stated in 1976) that the results of the ternary simulation of a gate network N correspond to the results of the binary race analysis of Ñ in the “Multiple-winner” model, where Ñ is the network N in which a delay has been inserted in each wire.
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