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Correspondence between ternary simulation and binary race analysis in gate networks

  • J. A. Brzozowski
  • C-J. Seger
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 226)

Abstract

Ternary simulation techniques provide efficient methods for the analysis of the behavior of VLSI circuits. However, the results of ternary simulation have not been completely characterized. In this paper we outline the proof of the Brzozowski-Yoeli conjecture (stated in 1976) that the results of the ternary simulation of a gate network N correspond to the results of the binary race analysis of Ñ in the “Multiple-winner” model, where Ñ is the network N in which a delay has been inserted in each wire.

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References

  1. [B84]
    R.E. Bryant, “A Switch-Level Model and Simulator for MOS Digital Systems”, IEEE Transactions on Computers, Vol. C-33, No. 2, Feb. 1984.Google Scholar
  2. [B83a]
    R.E. Bryant, “Race Detection in MOS Circuits by Ternary Simulation”, In F. Anceau and E.J. Aas (eds.), VLSI '83, pp. 85–95, Elsevier Science Publishers B. V. (North-Holland).Google Scholar
  3. [B83b]
    R.E. Bryant, “Toward a Proof of the Brzozowski-Yoeli Conjecture on Ternary Simulation”, Unpublished manuscript, Dec. 1983.Google Scholar
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    J.A. Brzozowski and C-J. Seger, “A Characterization of Ternary Simulation of Gate Networks”, Research Report CS-85-37, Department of Computer Science, University of Waterloo, Waterloo, Ontario, Canada, Oct. 1985.Google Scholar
  5. [B-Y]
    J.A. Brzozowski and M. Yoeli, “On a Ternary Model of Gate Networks”, IEEE Transactions on Computers, Vol. C-28, No. 3, pp. 178–183, Mar. 1979.Google Scholar
  6. [E]
    E.B. Eichelberger, “Hazard Detection in Combinational and Sequential Switching Circuits”, IBM J. Res. Dev., Vol. 9, pp. 90–99, Mar. 1965.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1986

Authors and Affiliations

  • J. A. Brzozowski
    • 1
  • C-J. Seger
  1. 1.Department of Computer ScienceUniversity of WaterlooWaterlooCanada

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