Test-pattern generation for VLSI circuits in a Prolog environment
Prolog eminently supports hierarchical development and mixing of descriptions at various hierarchical levels. This fact can be used in test-pattern generation by mixing the functional and implementation specifications of various modules. Only the modules that are faulty need to be expanded to their implementations and a functional description of all the other modules can be used, resulting in considerable gain in efficiency.
High-level fault injection can be easily implemented in Prolog by a hierarchical naming convention described in the paper.
Concurrent fault simulation can be viewed as an optimization of the Prolog control strategy and by saving some select (non-masking) results from previous computations, the wasteful recomputations can be avoided.
Subject IndexTesting Automatic test-pattern generation Logic programming Simulation
Unable to display preview. Download preview PDF.
- E. Ulrich, T. Baker, The Concurrent Fault Simulation of Nearly Identical Digital Networks, (Jun 1973), Design Automation Workshop Proc., pp 145–160, IEEE Computer, pp 39–44, (Apr 1974).Google Scholar
- M. R. Barbacci, G. E. Barnes, R. G. Cattell, D. P. Siewiorek, Symbolic Manipulation of Computer Descriptions: The ISPS Computer Description Language, Technical Report CMU-CS-79-137, Carnegie-Mellon University, Computer Science Department, (Aug 1979).Google Scholar
- M. R. Barbacci, W. B. Dietz, L. Szewerenko, Specification, Evaluation, and Validation of Computer Architecture Using Instruction Set Precessor Description, Technical Report CMU-CS-79-118, Carnegie-Mellon University, Computer Science Department, (1979).Google Scholar
- Kwok-Woon Lai, Functional Testing of Digital Systems, CMU-CS-81-148, Dept. of Computer Science, Carnegie-Mellon University, Pittsburgh, (Dec 1981).Google Scholar
- S. B. Akers, Functional Testing with Binary Decision Diagrams, Proceedings of 8th International Conference on Fault Tolerant Computing(FTCS-8), pp 75–82, IEEE Comp. Society, June 1978.Google Scholar
- S. M. Thatte, J. A. Abraham, Test generation for Microprocessors IEEE Trans. Comput., V C-29, (Jun 1980).Google Scholar
- P. W. Horstmann, Design for Testability using Logic Programming, IEEE International Conference, Cherry Hill, NJ, (Oct 1983).Google Scholar
- P. W. Horstmann, Functional Simulation using Logic Programming, TR-83-17, Syracuse University, Syracuse, NY, (Aug 1983).Google Scholar
- P. W. Horstmann, Expert Systems and Logic Programming for CAD, pp 37–46, VLSI Design, (Nov 1983).Google Scholar
- Norihisa Suzuki, Concurrent Prolog as an Efficient VLSI Design Language, pp 33–40, Computer, (Feb 1985).Google Scholar
- Fumihiro Maruyama, Masahiro Fujita, Hardware Verification, Computer, pp 22–32, (Feb 1985).Google Scholar
- W. F. Clocksin, C. S. Mellish, Programming in Prolog, Springer-Verlag, New York, NY, (1981).Google Scholar
- M. A. Breuer, A. D. Friedman, Diagnosis and Reliable Design of Digital Systems, Computer Society Press, Inc. 1976.Google Scholar