Parallel Prolog machine PARK: Its hardware structure and prolog system
In this paper we describe the hardware structure of PARK (is short for a PARallel processing system of Kobe university) and a parallel Prolog system, called PARK-Prolog, which will be implemented on this machine. PARK is a multi-microprocessor machine connected with a common bus. PARK is divided into one host processor and several (currently 3) slave processors. Each processor is composed of a 16 bit microprocessor (Motorola MC68000), a local memory, an address translation unit, and a common memory (the slave processor only). A broadcast operation can be performed on the common memory. The execution in PARK-Prolog exhibits AND parallelism, OR parallelism, and the combination both of them. PARK-Prolog equips a concurrent AND constructor and a parallel AND constructor for AND parallelism and a mode declaration for OR parallelism. The communication among processes is performed with a special built-in predicate through a communication channel.
KeywordsAccess Method Execution Model Address Translation Host Processor Hardware Structure
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