Axioms for memory access in asynchronous hardware systems
The problem of concurrent accesses to memory registers by asynchronous components is considered. A set of axioms about the values in a register during concurrent accesses is proposed. It is shown that if these axioms are met by a register then concurrent accesses to it may be viewed as nonconcurrent, thus making it possible to analyze asynchronous algorithms without elaborate timing analysis of operations. These axioms are shown, in a certain sense, to be the weakest. Motivation for this work came from analyzing low level hardware components in a VLSI chip which concurrently access a flip-flop.
KeywordsPartial Order Total Order Hardware Design Read Operation Memory Register
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