Advertisement

On mapping cube graphs onto VLSI arrays

  • I. V. Ramakrishnan
  • P. J. Varman
Session 5 VLSI
Part of the Lecture Notes in Computer Science book series (LNCS, volume 181)

Abstract

Formal models of linear, mesh and hexagonal arrays are presented. These arrays are well-suited for VLSI (very large scale integration). A model of a logical linear array, wherein adjacent processors may be separated by wires of arbitrary length, is also presented. Logical linear arrays are important computational structures suitable for implementation on a a wafer where fabrication errors may cause processors to be separated by arbitrarily long distances.

Cube graphs which are data-flow descriptions of some matrix and related computations are introduced. A mathematical technique is developed to construct algorithms for these array models from cube graphs. The technique is illustrated by constructing some published algorithms as well as some new algorithms.

Keywords

Linear Array Mapping Algorithm Input Port Reverse Edge Hexagonal Array 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    T.C. Chen, V.Y. Lum and C. Tung, “The Rebound Sorter: An efficient Sort Engine for Large Files,” Proceedings of the Fourth International Conference on Very Large Data Bases, (1978), pp. 312–318.Google Scholar
  2. [2]
    L.J. Guibas and F.M. Liang, “Systolic Stacks, Queues and Counters,” Proceedings of the MIT Conference on Advanced Research in VLSI, (January, 1982), pp. 155–164.Google Scholar
  3. [3]
    L. Johnsson and D. Cohen, “A Mathematical Approach to Modelling the Flow of Data and Control in Computational Networks,” VLSI Systems and Computations, H.T. Kung, R.F. Sproull, and G.L. Steele, Jr., (editors), Computer Science Press, (1981), pp. 213–225.Google Scholar
  4. [4]
    H.T. Kung, “Let's Design Algorithms for VLSI Systems,” Proceedings of the Caltech Conference on Very Large Scale Integration: Architecture, Design, Fabrication, (January, 1979), pp. 65–90.Google Scholar
  5. [5]
    H.T. Kung and C.E. Leiserson, “Systolic Arrays (for VLSI),” Sparse Matrix Proceedings 1978, I.S. Duff, and G.W. Stewart, (editors), SIAM, (1979), pp. 256–282.Google Scholar
  6. [6]
    H.T. Kung, “Why Systolic Architectures,” IEEE Computer 15(1), (January, 1980), pp. 37–46.Google Scholar
  7. [7]
    H.T. Kung and M. Lam, “Wafer-Scale Integration and Two-Level Pipelined Implementation of Systolic Arrays,” Proceedings of the MIT Conference on Advanced Research in VLSI, (January, 1984).Google Scholar
  8. [8]
    S.Y. Kung, “VLSI Array Processor for Signal Processing,” Proceedings of the MIT Conference on Advanced Research in Integrated Circuits, (January, 1980).Google Scholar
  9. [9]
    C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, (1980).Google Scholar
  10. [10]
    J.I Raffel, “On the Use of Nonvolatile Programming Links for Restructurable VLSI,” Proceedings of the Caltech Conference on VLSI, (January, 1979).Google Scholar
  11. [11]
    I.V. Ramakrishnan, D.S. Fussell and A. Silberschatz, “Systolic Matrix Multiplication on a Linear Array,” Twentieth Annual Allerton Conference on Computing, Control and Communication, (October, 1982).Google Scholar
  12. [12]
    I.V. Ramakrishnan, D.S. Fussell, and A. Silberschatz, “On Mapping Homogeneous Graphs on a Linear-Array Processor Model,” Proceedings of the 1983 International Conference on Parallel Processing, (August, 1983).Google Scholar
  13. [13]
    L. Snyder, “Introduction to the Configurable, Highly Parallel Computer,” IEEE Computer, 15(1), (January, 1982).Google Scholar
  14. [14]
    P.J. Varman, “Wafer-Scale Integration of Linear Processor Arrays,” Ph.D Dissertation, The University of Texas at Austin, (August, 1983).Google Scholar
  15. [15]
    P.J. Varman and D.S. Fussell, “Design of Robust Systolic Algorithms,” Proceedings of the 1983 International Conference on Parallel Processing, (August, 1983).Google Scholar
  16. [16]
    U. Weiser, and A. Davis, “A Wavefront Notation Tool for VLSI Array Design,” VLSI Systems and Computations, H.T. Kung, R.F. Sproull, and G.L. Steele, Jr., (editors), Computer Science Press, (1981), pp. 226–234.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1984

Authors and Affiliations

  • I. V. Ramakrishnan
    • 1
  • P. J. Varman
    • 2
  1. 1.Department of Computer ScienceUniversity of MarylandCollege Park
  2. 2.Department of Electrical EngineeringRice UniversityHouston

Personalised recommendations