Advertisement

VLSI systems for design rule checks

  • Rajiv Kane
  • Sartaj Sahni
Invited Talk
Part of the Lecture Notes in Computer Science book series (LNCS, volume 181)

Abstract

We develop VLSI designs for the solution of several problems that arise in the design rule check phase of design automation.

Keywords and Phrases

VLSI systems design rule checks rectilinear polygons systolic algorithms 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

6. References

  1. [ABRA82]
    M. Abramovici, Y. H. Levendel, and P. R. Menon, ”A Logic Simulation Machine” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 65–73 Google Scholar
  2. [BLAN81]
    Tom Blank, Mark Stefik, William vanCleemput ”A Parallel Bit Map Processor Architecture for DA Algorithms” ACM IEEE Eighteenth Design Automation Conference Proceedings pp 837–845 Google Scholar
  3. [CHYA83]
    Dah-Juh Chyan and Melvin A. Breuer, ”A Placement Algorithm for Array Processors” ACM IEEE 20th Design Automation Conference Proceedings pp 182–188 Google Scholar
  4. [DENN82]
    M. M. Denneau, ”The Yorktown Simulation Engine” CM IEEE Nineteenth Design Automation Conference Proceedings pp 55–59 Google Scholar
  5. [IOSU83]
    A. Iosupovici, C. King, and M. Breuer, ”A Module Interchange Machine” ACM IEEE 20th Design Automation Conference Proceedings pp 171–174 Google Scholar
  6. [KANE83]
    R. Kane, S. Sahni, ”A Systolic Design Rule Checker” TR 83-13, Department of Computer Science, University of Minnesota Google Scholar
  7. [KANE84a]
    R. Kane, S. Sahni, ”Systolic Algorithms for Rectilinear Polygons” TR 84-2, Department of Computer Science, University of Minnesota Google Scholar
  8. [KANE84b]
    R. Mane and S. Sahni, ”A hardware algorithm for net extraction”, University of Minnesota, Technical Report, 1984.Google Scholar
  9. [KRON82]
    E. Kronstadt and G. Pfister, ”Software Support for the Yorktown Simulation Engine” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 60–64 Google Scholar
  10. [KUNG79]
    H. T. Kung, ”Let's Design Algorithms for VLSI Systems” Proceedings of the CALTECH Conference on VLSI, January 1979, pp 65–90 Google Scholar
  11. [KUNG83]
    H. T. Kung, ”A Listing of Systolic Papers”, Department of Computer Science, Carnegie-Mellon University Google Scholar
  12. [LEIS79]
    C. E. Leiserson, ”Systolic Priority Queues” Proceedings of Conference on VLSI: Architecture, Design, Fabrication California Institute of Tachnology Jan 79 pp 199–214 Google Scholar
  13. [MUDG82]
    T. N. Mudge, R. A. Ratenbar, R. M. Lougheed, and D. E. Atkins, ”Cellular Image Processing Techniques for VLSI Circuit Layout Validation and Routing” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 537–543 Google Scholar
  14. [NAIR82]
    R. Nair, S. Jung, S. Liles, and R. Villani, ”Global Wiring on a Wire Routing Machine” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 224–231 Google Scholar
  15. [PFIS82]
    G. F. Pflster, ”The Yorktown Simulation Engine, Introduction” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 51–54 Google Scholar
  16. [SEIL82]
    L. Seiler, ”A Hardware Assisted Design Rule Check Architecture” ACM IEEE Nineteenth Design Automation Conference Proceedings pp 232–238 Google Scholar
  17. [UEDA83]
    Kazuhiro Ueda, Tsutomu Komatsubara and Tsutomu Hosaka, ”A Parallel Processing Approach for Logic Module Placement” ACM IEEE Transactions on Computer Aided Design Vol. CAD-2 No.1 Jan.83 pp 39–47 Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1984

Authors and Affiliations

  • Rajiv Kane
    • 1
  • Sartaj Sahni
    • 1
  1. 1.University of MinnesotaUSA

Personalised recommendations