A hardware implementation of the CSP primitives and its verification

  • Dorit Ron
  • Flavia Rosemberg
  • Amir Pnueli
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 172)


A design for a hardware interface that implements CSP-like communication primitives is presented. The design is based on a bus scheme that allows processes to “eavesdrop” on messages not directly addressed to them. A temporal logic specification is given for the network and an outline of a verification proof is sketched.


Temporal Logic Hardware Implementation Associative Memory Proof System Safety Property 
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8. References

  1. [H]
    C.A.R. Hoare “Communicating Sequential Processes', Communications of the ACM, Vol. 21, No. 8, 666–677, August 1978.Google Scholar
  2. [MP1]
    Z. Manna and A. Pnueli, “Verification of Concurrent Programs: Temporal Proof Principles”, Proc. of the Workshop on Logic of Programs (D. Kozen, ed.), Yorktown Heights, NY (1981).Google Scholar
  3. [MP2]
    Z. Manna and A. Pnueli, “Verification of Concurrent Programs: A Temporal Proof System”, Proc. 4th School on Advanced Programming, Amsterdam, The Netherlands (June 1982).Google Scholar
  4. [R]
    D. Ron, “Temporal Verification of Communication Protocols”, M.Sc. Thesis, Weizmann Institute.Google Scholar
  5. [Ros]
    F. Rosemberg, “Final Report”, Dept. of Applied Mathematics, The Weizmann Institute of Science, July 1983.Google Scholar
  6. [RRP]
    D. Ron, F. Rosemberg and A. Pnueli, “Verification of a Hardware Implementation of the CSP Primitives”. In preparation.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1984

Authors and Affiliations

  • Dorit Ron
    • 1
  • Flavia Rosemberg
    • 1
  • Amir Pnueli
    • 1
  1. 1.Department of Applied MathematicsWeizmann InstituteRehovotIsrael

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