Area-time optimal vlsi integer multiplier with minimum computation time

  • K. Mehlhorn
  • F. P. Preparata
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 172)


According to VLSI theory, [logn, √n] is the range of computation times for which there may exist an AT2-optimal multiplier of n-bit integers. Such networks were previously known for the time range [Ω(log2n), 0(√n)]; in this paper we settle this theoretical question, by exhibiting a-class of AT2-optimal multipliers with computation times [Ω(logn), 0(n1/2)]. Our designs are based on the DFT on a Fermat ring, whose elements are represented in a redundant radix-4 form to ensure 0(1) addition time.


Discrete Fourier Transform Shift Register Cyclic Shift Fermat Ring Integer Multiplication 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1984

Authors and Affiliations

  • K. Mehlhorn
  • F. P. Preparata

There are no affiliations available

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