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The VLSI revolution in theoretical circles

  • Arnold L. Rosenberg
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 172)

Abstract

Presented in these pages are personal observations concerning the effect that Very Large Scale Integrated circuit technology (VLSI) has had on the Theoretical Computer Science field and community, together with some guesses as to why this technological advance has had so much more profound an effect on the Community than have had numerous earlier technological advances. The tale spun includes some sociology, some technology, and some history — as well as some theoretical material, mostly as illustration.

Keywords

Systolic Array Very Large Scale Integrate Array Logic Circuit Layout Very Large Scale Integrate Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    R. Aleliunas and A.L. Rosenberg (1980): On embedding rectangular grids in square grids. IEEE Trans. Comp., C-31, 907–913.Google Scholar
  2. 2.
    A.J. Atrubin (1965): A one-dimensional real-time iterative multiplier. IEEE Trans. Elec. Comp., EC-14, 394–399.Google Scholar
  3. 3.
    B.S. Baker, S.N. Bhatt, F.T. Leighton (1983): An approximation algorithm for Manhattan routing. 15th ACM Symp. on Theory of Computing, 477–486.Google Scholar
  4. 4.
    B.S. Baker and R.Y. Pinter (1983): An algorithm for the optimal placement and routing of a circuit within a ring of pads. 24th IEEE Symp. on Foundations of Computer Science, 360–370.Google Scholar
  5. 5.
    Z. Barzilai, J.L. Carter, A.K. Chandra, B.K. Rosen (1983): Diagnosis based on signature testing. IBM Report RC-9682.Google Scholar
  6. 6.
    Z. Barzilai, D. Coppersmith, A.L. Rosenberg (1983): Exhaustive bit-pattern generation, with applications to VLSI self-testing. IEEE Trans. Comp., C-32, 190–194.Google Scholar
  7. 7.
    G.M. Baudet, F.P. Preparata, J.E. Vuillemin (1983): Area-time optimal VLSI circuits for convolution. IEEE Trans. Comp., C-32, 684–688.Google Scholar
  8. 8.
    R.P. Brent and H.T. Kung (1980): The chip complexity of binary arithmetic. 12th ACM Symp. on Theory of Computing, 190–200.Google Scholar
  9. 9.
    M.L. Brady and D.J. Brown (1984): Arbitrary planar routing with four layers. 1984 MIT Conf. on Advanced Research in VLSI, 194–201.Google Scholar
  10. 10.
    D.J. Brown and R.L. Rivest (1981): New lower bounds for channel width. VLSI Systems and Computations (ed. H.T. Kung, B. Sproull, G. Steele) Computer Science Press, Rockville, MD, pp.178–185.Google Scholar
  11. 11.
    R.E. Bryant (1981): A switch-level model of MOS logic circuits. VLSI 81: Very Large Scale Integration (ed. J.P. Gray) Academic Press, London, pp. 329–340.Google Scholar
  12. 12.
    J.L. Carter (1982): The theory of signature testing for VLSI. 14th ACM Symp. on Theory of Computing, 66–76.Google Scholar
  13. 13.
    J.L. Carter and M.N. Wegman (1979): Universal classes of hash functions. J. CSS 18, 143–154.Google Scholar
  14. 14.
    B. Chazelle and L. Monier (1981): A model of computation for VLSI with related complexity results. 13th ACM Symp. on Theory of Computing, 318–325.Google Scholar
  15. 15.
    F.R.K. Chung, F.T. Leighton, A.L. Rosenberg (1983): DIOGENES — A methodology for designing fault-tolerant processor arrays. 13th Intl. Conf. on Fault-Tolerant Computing, 26–32.Google Scholar
  16. 16.
    F.R.K. Chung, F.T. Leighton, A.L. Rosenberg (1984): Embedding graphs in books: A layout problem with applications to VLSI design. Typescript.Google Scholar
  17. 17.
    A. Cobham (1966): The recognition problem for the set of perfect squares. Proc. 7th IEEE Symp. on Switching and Automata Theory, 78–87.Google Scholar
  18. 18.
    S.N. Cole (1969): Real-time computation by n-dimensional iterative arrays of finite-state machines. IEEE Trans. Comp., C-18, 349–365.Google Scholar
  19. 19.
    S.A. Cook and S.O. Aanderaa (1969): On the minimum computation time of functions. Trans. AMS 142, 291–314.Google Scholar
  20. 20.
    J.A. Darringer, W.H. Joyner, C.L. Berman, L. Trevillyan (1981): Logic synthesis through local transformations. IBM Report RC-8748.Google Scholar
  21. 21.
    P.W. Dymond and S.A. Cook (1980): Hardware complexity and parallel computation. Proc. 21st IEEE Symp. on Foundations of Computer Science, 360–372.Google Scholar
  22. 22.
    E.B. Eichelberger and T.W. Williams (1978): A logic design structure for LSI testability. J. Design Automation and Fault-Tolerant Comp. 2, 165–178.Google Scholar
  23. 23.
    S. Even and A. Itai (1971): Queues, stacks, and graphs. In Theory of Machines and Computations (Z. Kohavi and A. Paz eds.) Academic Press, NY, pp. 71–86.Google Scholar
  24. 24.
    H. Fleisher and L.I. Maissel (1975): An introduction to array logic. IBM J. Res. Dev. 19, 98–109.Google Scholar
  25. 25.
    M.J. Foster and H.T. Kung (1980): The design of special-purpose VLSI chips. Computer 13, 26–40.Google Scholar
  26. 26.
    M.J. Foster and H.T. Kung (1981): Recognize regular languages with programmable building-blocks. In VLSI 81: Very Large Scale Integration (ed. J.P. Gray) Academic Press, London, pp. 75–84.Google Scholar
  27. 27.
    A. Frank (1982): Disjoint paths in a rectilinear grid. Combinatorica, to appear.Google Scholar
  28. 28.
    M. Furst, J.B. Saxe, M. Sipser (1983): Parity, circuits, and the polynomial-time hierarchy. Math. Syst. Theory, to appear.Google Scholar
  29. 29.
    F.C. Hennie (1965): One-tape, off-line Turing machine computations. Inform. Contr. 8, 553–578.Google Scholar
  30. 30.
    R.M. Karp, F.T. Leighton, R.L. Rivest, C.D. Thompson, U. Vazirani, V. Vazirani (1983): Global wire routing in two-dimensional arrays. 24th IEEE Symp. on Foundations of Computer Science, 453–459.Google Scholar
  31. 31.
    H.T. Kung (1983): Systolic algorithms and their implementation. Typescript.Google Scholar
  32. 32.
    H.T. Kung and C.E. Leiserson (1980): Systolic arrays (for VLSI). In Chapter 8 of (Mead-Conway, 1980).Google Scholar
  33. 33.
    H.T. Kung and R.L. Picard (1984): One-dimensional systolic arrays for multi-dimensional convolution and resampling. In VLSI for Pattern Recognition and Image Processing, Springer-Verlag.Google Scholar
  34. 34.
    A.S. LaPaugh and R.J. Lipton (1983): Total stuck-at fault testing by circuit transformation. 20th ACM-IEEE Design Automation Conf. Google Scholar
  35. 35.
    F.T. Leighton (1984): Parallel computation using meshes of trees. 1983 Workshop on Graph-Theoretic Concepts in Computer Science, 200–218.Google Scholar
  36. 36.
    F.T. Leighton and A.L. Rosenberg (1983): Automatic generation of three-dimensional circuit layouts. 1983 IEEE Intl. Conf. on Computer Design, 633–636.Google Scholar
  37. 37.
    F.T. Leighton and A.L. Rosenberg (1984): Three-dimensional circuit layouts. Submitted for publication.Google Scholar
  38. 38.
    C.E. Leiserson, F.M. Rose, J.B. Saxe (1982): Digital circuit optimization. 3rd Caltech Conf. on VLSI. Google Scholar
  39. 39.
    T. Lengauer (1982): The complexity of compacting hierarchically specified layouts of integrated circuits. 23rd IEEE Symp. on Foundations of Computer Science, 358–368.Google Scholar
  40. 40.
    T. Lengauer (1983): On the solution of inequality systems relevant to IC-layout. J. Algorithms, to appear.Google Scholar
  41. 41.
    T. Lengauer (1984): Efficient algorithms for the constraint generation for integrated circuit layout compaction. 1983 Workshop on Graph-Theoretic Concepts in Computer Science, 219–230.Google Scholar
  42. 42.
    T. Lengauer and K. Mehlhorn (1984): The HILL system: a design environment for the hierarchical specification, compaction, and simulation of integrated circuit layouts. 1984 MIT Conf. on Advanced Research in VLSI, 139–149.Google Scholar
  43. 43.
    T. Lengauer and S. Naeher (1984): Delay-independent switch-level simulation of digital MOS circuits. Typescript.Google Scholar
  44. 44.
    R.J. Lipton and R. Sedgewick (1981): Lower bounds for VLSI. 13th ACM Symp. on Theory of Computing, 300–307.Google Scholar
  45. 45.
    O.B. Lupanov (1961): On the realization of functions of logical algebra by formulae of limited depth in the basis [AND, OR, NOT]. Probl. Kibernetiki 6, 5–14.Google Scholar
  46. 46.
    C. Mead and L. Conway (1980): Introduction to VLSI Systems, Addison-Wesley, Reading, MA.Google Scholar
  47. 47.
    K. Mehlhorn and F.P. Preparata (1983): Routing through a rectangle. Typescript.Google Scholar
  48. 48.
    Th. Ottmann, A.L. Rosenberg, L.J. Stockmeyer (1981): A dictionary machine (for VLSI). IEEE Trans. Comp., C-31, 892–897.Google Scholar
  49. 49.
    F.P. Preparata (1981): Optimal three-dimensional VLSI layouts. Math. Systems Theory 16, 1–8.Google Scholar
  50. 50.
    F.P. Preparata (1983): A mesh-connected area-time optimal VLSI multiplier of large integers. IEEE Trans. Comp., C-32, 194–198.Google Scholar
  51. 51.
    F.P. Preparata and W. Lipski (1982): Optimal three-layer channel routing. 23rd IEEE Symp. on Foundations of Computer Science 350–357.Google Scholar
  52. 52.
    F.P. Preparata and J.E. Vuillemin (1980): Area-time optimal VLSI networks for multiplying matrices. Inf. Proc. Let. 11, 77–80.Google Scholar
  53. 53.
    F.P. Preparata and J.E. Vuillemin (1981): The cube-connected cycles: a versatile network for parallel computation. C. ACM 24, 300–309.Google Scholar
  54. 54.
    M.O. Rabin (1963): Real-time computation. Israel J. Math. 1, 203–211.Google Scholar
  55. 55.
    S.P. Reiss and J.E. Savage (1982): SLAP — A methodology for silicon layout. IEEE Int'l. Conf. on Circuits and Computers, 281–285.Google Scholar
  56. 56.
    R.L. Rivest, A.E. Baratz, G. Miller (1981): Provably good channel routing algorithms. VLSI Systems and Computations (ed. H.T. Kung, B. Sproull, G. Steele) Computer Science Press, Rockville, MD, pp. 153–159.Google Scholar
  57. 57.
    R.L. Rivest and C.M. Fiduccia (1982): A "greedy" channel router. 19th ACM-IEEE Design Automation Conf., 418–424.Google Scholar
  58. 58.
    A.L. Rosenberg (1981): Three-dimensional integrated circuitry. In VLSI Systems and Computations (ed. H.T. Kung, B. Sproull, G. Steele) Computer Science Press, Rockville, MD, pp. 69–80.Google Scholar
  59. 59.
    A.L. Rosenberg (1981): Routing with permuters: Toward reconfigurable and fault-tolerant networks. Duke Univ. Tech. Rpt. CS-1981-13.Google Scholar
  60. 60.
    A.L. Rosenberg (1983): Three-dimensional VLSI: A case study. J. ACM 30, 397–416.Google Scholar
  61. 61.
    A.L. Rosenberg (1983): The Diogenes approach to testable fault-tolerant arrays of processors. IEEE Trans. Comp., C-32, 902–910.Google Scholar
  62. 62.
    A.L. Rosenberg (1984): Fault-tolerant interconnection networks: a graph-theoretic approach. 1983 Workshop on Graph-Theoretic Concepts in Computer Science, 286–297.Google Scholar
  63. 63.
    A.L. Rosenberg (1984): On designing fault-tolerant VSLI processor arrays. Advances in Computing Research 2, to appear.Google Scholar
  64. 64.
    W.L. Ruzzo and L. Snyder (1981): Minimum edge-length planar embeddings of trees. VLSI Systems and Computations (ed. H.T. Kung, B. Sproull, G. Steele) Computer Science Press, Rockville, MD, pp. 119–123.Google Scholar
  65. 65.
    M. Sarrafzadeh and F.P. Preparata (1983): Compact channel-routing of multiterminal nets. Typescript.Google Scholar
  66. 66.
    J.E. Savage (1981): Area-time tradeoffs for matrix multiplication and related problems in VLSI models. J. CSS, 230–242.Google Scholar
  67. 67.
    J.E. Savage (1981): Planar circuit complexity and the performance of VLSI algorithms. In VLSI Systems and Computations (ed. H.T. Kung, B. Sproull, G. Steele) Computer Science Press, Rockville, MD, pp. 61–68.Google Scholar
  68. 68.
    J.E. Savage (1982): Multilective planar circuit size. 20th Allerton Conf. on Commun., Control, and Computing.Google Scholar
  69. 69.
    J.E. Savage (1983): Three VLSI compilation techniques: PLAs, Weinberger arrays, and SLAP, a new silicon layout program. In Algorithmically-Specialized Computers (ed. L. Snyder, L.J. Siegel, H.J. Siegel, D. Gannon) Academic Press, NY.Google Scholar
  70. 70.
    J.E. Savage (1983): Heuristics in the SLAP layout system. 1983 IEEE Intl Conf. On Computer Design, 637–640.Google Scholar
  71. 71.
    J.C. Shepherdson (1959): The reduction of two-way automata to one-way automata. IBM J. Res. Dev. 3, 198–200.Google Scholar
  72. 72.
    L. Snyder (1980): A synopsis of the Blue CHiP Project. Purdue Univ. Dept. of Computer Science Tech. Rpt.Google Scholar
  73. 73.
    L. Snyder (1981): Overview of the CHiP computer. In VLSI 81: Very Large Scale Integration (ed. J. P. Gray) Academic Press, London, pp. 237–246.Google Scholar
  74. 74.
    R.E. Tarjan (1972): Sorting using networks of queues and stacks. J.ACM 19, 341–346.Google Scholar
  75. 75.
    C.D. Thompson (1980): A complexity theory for VLSI. Ph.D. Thesis, Carnegie-Mellon University; see also Area-time complexity for VLSI. 11th ACM Symp. on Theory of Computing, 1979, 81–88.Google Scholar
  76. 76.
    J. Vuillemin (1983): A combinatorial limit to the computing power of VLSI circuits. IEEE Trans. Comp., C-32, 294–300.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1984

Authors and Affiliations

  • Arnold L. Rosenberg
    • 1
    • 2
  1. 1.Department of Computer ScienceDuke UniversityDurhamUSA
  2. 2.Microelectronics Center of North Carolina Research Triangle ParkUSA

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