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Computer algebra and VLSI, prospects for cross fertilization

System Oriented Applications
Part of the Lecture Notes in Computer Science book series (LNCS, volume 162)

Abstract

Experimental single-chip LISP processors are already being build, but high performance processor-intensive architectures, which might be used for CPU-intensive tasks in computer algebra are still in the early stages of design. Parallelism will be needed to extend the power of computer algebra systems. Implementation of a parallel EVAL scheme is one of the most frequently mentioned options. The implementation of special purpose parallel hardware with a thight coupling between storage and computational units, was proposed recently under the name systolic array. The actual introduction of a flexible, general purpose, processor-intensive computer partition as a part of a large scale multiprocessor Computer Algebra system, depends heavily on the progress made in design and technology needed to develop these computational structures. This paper describes ideas for the design of a fully programmable processor-intensive computer partition, which can be (micro)programmed from a high level language.

Keywords

Digital Signal Processing Computer Algebra Computer Algebra System Systolic Array Single Instruction Multiple Data 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Marti, J. and Fitch, J. P., "The Bath Concurrent LISP Machine", These proceedings.Google Scholar
  2. [2]
    Sussmann, G. J. et al. Scheme 79, LISP on a chip, IEEE Computer, Vol 14, no 7. July 1981, pp 10–21.Google Scholar
  3. [3]
    Patterson, D. A. and Ditzel, D. R., The case for the Reduced Instruction Set Computer. Computer Architecture News, October 1980.Google Scholar
  4. [4]
    Patterson, D. A. and Sequin, C. H., Risc I: A Reduced Instruction Set VLSI Computer. Proceedings of the Eighth Annual Symposium on Computer Architecture (May 1981), Minneapolis Minnesota, pp 443–457.Google Scholar
  5. [5]
    Thompson, J. S. and Tewksbury S. K., LSI Signal Processor Architecture for Telecommunication applications. IEEE Acoustics Speech and Signal Processing, ASSP-30, number 4., pp 613–631.Google Scholar
  6. [6]
    Nishitani, T. et. al., A single chip digital signal processir for telecommunication applications. IEEE Journal of Solid-State Circuits, Vol. SC-16 (1981), pp 372–376.Google Scholar
  7. [7]
    NEC Catalog uPD7720 Digital Signal Processor, pp 519.Google Scholar
  8. [8]
    Smit, J., Herrmann, O.E. and Bredero, R., Microprogramming from a High Level Language, theory and practice. Twente University of Technology Research Report 1231-AM-0683.Google Scholar
  9. [9]
    Smit, J., Herrmann, O.E. and Jansen, J. H., Flexible Tools to Microprogram Signalprocessors. Twente University of Technology Research Report 1231-AM-2282.Google Scholar
  10. [10]
    Kung, H.T., Use of VLSI in Algebraic Computation, Some suggestions. Proceedings of the 1981 ACM Symposium on Symbolc and Algebraic Computation. pp. 218–222.Google Scholar
  11. [11]
    Piloty, R., Barbacci, M., Borrione D., Dietmeyer, D., Hill, F. and Skelly, P. "CONLAN-A Formal Construction Method for Hardware Description Languages, Basic principles, Language derivation, Language application", Proc. of the Nactional Computer Conference 1980, Vol 49, Anaheim, California, pp 209–236.Google Scholar
  12. [12]
    Special issue on Hardware Description languages, IEEE Computer Society, Computer, Vol. 10, No. 6., June 1977.Google Scholar
  13. [13]
    Lim, W.Y.P., "HISDL, A structure description language". Comm. of the ACM, Vol. 25, no 11, pp. 823–831.Google Scholar
  14. [14]
    Van Hulzen, J.A., Hulshof, B.J.A., Smit, J., "Code optimization facilities in the NETFORM context". Twente University of Technology: Memorandum nr.TW-368.Google Scholar
  15. [15]
    Van Hulzen, J.A., Breuers grow factor algorithm in computer algebra. Proc. of the 1981 ACM Symposium on Symbolic and Algebraic computation. pp. 100–105. (1981).Google Scholar

Copyright information

© Springer-Verlag 1983

Authors and Affiliations

  • J Smit
    • 1
  1. 1.Dep. of Electrical Eng., EF9274Twente University of TechnologyEnschedeThe Netherlands

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