Computer algebra and VLSI, prospects for cross fertilization

System Oriented Applications
Part of the Lecture Notes in Computer Science book series (LNCS, volume 162)


Experimental single-chip LISP processors are already being build, but high performance processor-intensive architectures, which might be used for CPU-intensive tasks in computer algebra are still in the early stages of design. Parallelism will be needed to extend the power of computer algebra systems. Implementation of a parallel EVAL scheme is one of the most frequently mentioned options. The implementation of special purpose parallel hardware with a thight coupling between storage and computational units, was proposed recently under the name systolic array. The actual introduction of a flexible, general purpose, processor-intensive computer partition as a part of a large scale multiprocessor Computer Algebra system, depends heavily on the progress made in design and technology needed to develop these computational structures. This paper describes ideas for the design of a fully programmable processor-intensive computer partition, which can be (micro)programmed from a high level language.


Digital Signal Processing Computer Algebra Computer Algebra System Systolic Array Single Instruction Multiple Data 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag 1983

Authors and Affiliations

  • J Smit
    • 1
  1. 1.Dep. of Electrical Eng., EF9274Twente University of TechnologyEnschedeThe Netherlands

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