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R.P.Brent and H.T.Kung, "The Chip Complexity of Binary Arithmetic," Proc. 12th Annu. ACM Symp. on Theory of Comput., ACM, pp.190–200, April 1980.
R.P. Brent and H.T. Kung, "On the Area of Binary Tree Layouts," Information Processing Letters, Vol.11, No.1, pp.46–48, Aug. 1980.
B.Chazelle and L.Monier, "A Model of Computation for VLSI with Related Complexity Results," Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, Pa., Tech. Rep. CMU-CS-81-107, Feb. 1981.
I.Deegan, "Concise Cellular Array for Multiplication and Division," Electronics Letters, Vol.7, No.23, Nov. 1971.
R.B. Johnson Jr., "The Complexity of a VLSI Adder," Information Processing Letters, Vol.11, No.2, pp.92–93, Oct. 1980.
D.E. Knuth, The Art of Computer Programming, Vol.3: Sorting and Searching, Addison-Wesley, Reading, Massachusetts, 1973.
R.J. Lipton and R.E. Tarjan, "Applications of a Planar Separator Theorem," SIAM J., Vol.9, No.3, pp.615–627, Aug. 1980.
K. Menger, "Zur Allgemeinen Kurventheorie," Fund. Math., Vol.10, pp.96–115, 1927.
J.E. Savage, The Complexity of Computing, Wiley-Interscience, New York, N.Y., 1976.
J.E.Savage, "Area-Time Tradeoffs for Matrix Multiplication and Related Problems in VLSI Models," Dept. of Comput. Sci., Brown Univ., Priovidence, R.I., Tech. Rep. CS-50, Aug. 1979.
J.E.Savage, "Planar Circuit Complexity and the Performance of VLSI Algorithms," INRIA Rapports de Recherche, No.77, April 1981.
C.D.Thompson, "A Complexity Theory for VLSI," Dept. of Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, Pa., Tech. Rep. CMU-CS-80–140, Aug. 1980.
J.Vuillemin, "A Combinational Limit to the Computing Power of V.L.S.I. Circuits," IEEE 21st Annu. Symp. on FOCS, pp.294–300, Oct. 1980.
K. Wada, K. Hagihara and N. Tokura, "The Area-Time Complexity of n Variables Logical Functions," Trans. IECE Japan, Vol.J64-D, No.8, pp.676–681, Aug. 1981 (in Japanese).
K. Wada, K. Hagihara and N. Tokura, "The Area Complexity on a VLSI Model," Trans. IECE Japan, Vol. J65-D, No.4, pp.478–485, April 1982 (in Japanese).
K. Wada, K. Hagihara and N. Tokura, "Area and Time Complexities of VLSI Computations," Proc. of the 7th IBM Symp. on Math. Foundations of Comput. Sci., Math. Theory of Computations, IBM Japan, June 1982.
K.Wada, K.Hagihara and N.Tokura, "The Area Lower Bounds of Combinational Circuits on a VLSI Model," Papers of Tech. Group on Automat. and Lang., AL82-30, IECE Japan, Sept. 1982 (in Japanese).
H.Yasuura and S.Yajima, "On Embedding Problems of Logic Circuits in a VLSI Model," Papers of Tech. Group on Automat. and. Lang., AL81-49, IECE Japan, Sept. 1981 (in Japanese).
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© 1983 Springer-Verlag Berlin Heidelberg
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Hagihara, K., Wada, K., Tokura, N. (1983). Effects of practical assumption in area complexity of VLSI computation. In: Goto, E., Furukawa, K., Nakajima, R., Nakata, I., Yonezawa, A. (eds) RIMS Symposia on Software Science and Engineering. Lecture Notes in Computer Science, vol 147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-11980-9_20
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DOI: https://doi.org/10.1007/3-540-11980-9_20
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