Area-time optimal VLSI networks for computing integer multiplication and Discrete Dourier Transform

  • F. P. Preparata
  • J. E. Vuillemin
Session 1: A. Paz, Chairman
Part of the Lecture Notes in Computer Science book series (LNCS, volume 115)


In this paper we present a class of VLSI networks for computing the Discrete Fourier Transform and the product of two N-bit integers. These networks match, within a constant factor, the known theoretical lower-bound O(N2) to the area × (time)2 measure of complexity. While this paper's contribution is mainly theoretical, it points toward very practical directions: we show how to design multipliers with area A = O(N) and time T=O(√N) on one hand, and A=0((N/log2N)2), T = O(log2N) on the other. Both of these designs should be contrasted with the currently available multipliers, whose performances are A=O(N), T=O(N) or even A=O(N2), T=O(N).


Integer Multiplication Horizontal Wire Pipeline Operation Cyclic Convolution Linear Systolic Array 
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Copyright information

© Springer-Verlag Berlin Heidelberg 1981

Authors and Affiliations

  • F. P. Preparata
    • 1
  • J. E. Vuillemin
    • 2
  1. 1.the Coordinated Science LaboratoryUniversity of IllinoisUrbana
  2. 2.the Laboratorie de Recherche en InformatiqueUniversité de Paris-SudOrsayFrance

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